Datasheet
Application Information
13−2
SLLS535E − April 2008TUSB6250
13.2 Reset Timing Reference
There are two requirements for the reset signal timing.
• The minimum reset pulse width is 100 µs at power up. This time is measured from the time the power
ramps up to 90% of the nominal V
DD
, until the reset signal is no longer active (reset is active as long as
it is less than 1.2 V).
• The clock must be valid during the last 60 µs of the reset window. The clock is valid when the oscillation
on the XTAL2 pin exceeds 1.2 Vp-p.
Figure 13−1 illustrates the relationship between the power, reset, and clock signals. Note that when using a
24-MHz crystal and the on-chip oscillator, the clock signal may take about 1 ms to ramp up, become valid, and
stablize after power up. Therefore, it is recommended to extend the reset window to 2 ms or more to ensure
that there is at least a 60-µs overlap with a valid clock. Extending the reset longer than 2 ms is fine; however,
this reduces the time available for the firmware to download the descriptor and application code from the
external I
2
C EEPROM. This must be considered during development, because the USB 2.0 specification
requires all bus-powered USB devices to finish the reset and start signaling connection to the upstream USB
host or hubs within 100 ms after drawing power from VBUS. The reset signal is inactive when it goes above
1.8 V.
CLK
t
Reset
3.3 V
1.8 V
1.2 V
0 V
V
CC
90%
Reset Time < 100 ms
Reset Time > 100 µs
> 60 µs
Figure 13−1. Controller Reference Reset Timing Diagram
13.3 Supply Voltage Ramp Time
The 3.3-V supply voltages (AVDD and DVDD) must ramp from 0 V to 2.5 V in 650 µs or less as noted in the
recommended operating conditions. If the 3.3-V supply voltages ramp too slowly, the internal 1.8-V voltage
regulators turn on before there is enough voltage to drive them to 1.8 V. This can cause the internal PLL
circuitry powered by PLLVDD18 to become unstable. The PLL instability draws a lot of current which forces
the voltage level of the PLLVDD18 power rail to remain at 1.4 V instead of 1.8 V thus keeping the PLL unstable.
In the case that the AVDD and DVDD supply voltages are supplied separately in a design, it is the ramp time
of the AVDD supply voltage that will impact the PLLVDD18 power rail. Please note that the recommend 3.3-V
supply voltages (AVDD and DVDD) ramp time from 0 V to 2.5 V is typically met without any issue in TUSB6250
applications that are USB bus powered.