Datasheet

Electrical Specifications
12−1
SLLS535E − April 2008 TUSB6250
12 Electrical Specifications
12.1 Absolute Maximum Ratings
†
Supply voltage, V
DD
−0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
, 3.3-V LVCMOS −0.5 V to V
DD
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-V failsafe TTL-compatible LVCMOS −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, V
O
, 3.3-V LVCMOS −0.5 V to V
DD
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-V failsafe TTL-compatible LVCMOS −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
12.2 Recommended Operating Conditions
PARAMETER MIN TYP MAX UNIT
V
DD
Supply voltage
†
3 3.3 3.6 V
V
I
Input voltage
LVCMOS 0 V
DD
V
V
I
Input voltage
5-V failsafe TTL-compatible LVCMOS
0 5.5
V
V
O
Output voltage

LVCMOS 0 V
DD
V
V
O
Output voltage

5-V failsafe TTL-compatible LVCMOS 0 5.5 V
V
IH
High-level input voltage
LVCMOS 0.7 V
DD
V
V
IH
High-level input voltage
5-V failsafe TTL-compatible LVCMOS
2
V
V
IL
Low-level input voltage
LVCMOS 0 0.3 V
DD
V
V
IL
Low-level input voltage
5-V failsafe TTL-compatible LVCMOS
0 0.8
V
T
A
Operating temperature 0 70 °C
T
J
Virtual junction temperature

Low-K board, R
θJA
= 87.41 °C/W, T
A
70°C 93
°C
T
J
Virtual junction temperature

High-K board, R
θJA
= 59.95 °C/W, T
A
70°C 86
°
C
t
r
3.3-V power supply voltage rise time (0 V to 2.5 V) for DV
DD
and AV
DD
50 250 650 µs
†
Applies to both digital core supply voltage DVDD and integrated Phy’s supply voltage AVDD. Does not apply to any 1.8-V supply voltage that
is provided through the internal voltage regulator.
‡
Although the 5-V failsafe TTL compatible LVCMOS output buffer can only drive up to V
DD
, it can be pulled up to 5.5 V through the weak pullup
resistor when its output buffer is turned off.
§
The junction temperature listed reflects simulation conditions. The customer is responsible for verifying the junction temperature. The R
θJA
value
is measured at an airflow speed of zero ft/min.