Datasheet

ATA/ATAPI Interface Port
11−24
SLLS535E − March 2008TUSB6250
BIT FUNCTIONRESETNAME
4 BUFOVFLOW 0 Internal buffer overflow error.
The internal buffer refers to the 6-byte internal buffer space outside of sector FIFO designed
to handle extra data that may be received from the ATA/ATAPI device in pausing a UDMA
read operation.
This bit, when set, indicates that the 6-byte internal data buffer experienced overflow (more
than 6 bytes of data are transferred into this 6-byte internal buffer space after either sector
FIFO full or expected transfer byte count is reached for current auto-data transfer).
This bit can be used in all nonmanual data transfer modes, which include both read and write
data transfers. It may be useful in UDMA-read data transfer as error indication. For PIO or
multiword DMA data transfer, BUFOVFLOW should not happen, unless a hardware logic
error occurred. In such case, this bit is useful for debugging.
For a read transfer, the BUFOVFLOW could happen when the following cases occur:
 The sector FIFO is full, however the expected byte count has not been reached yet.
For a write transfer, the BUFOVFLOW can only happen in a hardware logic error condition:
 The TUSB6250 is sending the data normally to the ATA/ATAPI device; however, a device
error causes it to pause and terminate the current data transfer. This bit is set if a hardware
logic error occurs, such that the TUSB6250 ATA/ATAPI state machine doesn’t respond
to the ATA/ATAPI device’s pause and termination request. This bit is useful to debug this
rare case.
The MCU can set either the SOFT_RST bit or the START_ATAPI bit in the ATA/ATAPI
interface configuration register to 1 to clear the BUFOVFLOW bit.
5 SYNBUF_RCVERR 0 Ultra DMA receive synch-buffer error (for UDMA-read-only)
This bit, when set, indicates that the synch buffer for the ultra DMA receive operation has an
overrun error. This error may occur when the ATA/ATAPI device bursts data at a transfer rate
faster than 120 MBps.
The MCU can set either the SOFT_RST bit or the START_ATAPI bit in the ATA/ATAPI
interface configuration register 1 to clear the SYNBUF_RCVERR bit.
6 ULTRA_RCVEX 0 Ultra DMA receive extra (for UDMA-read-only).
This bit, when set, indicates several extra bytes of data were received after the TUSB6250
received the expected number of bytes from the ATA/ATAPI device. These extra bytes are
received at the time period between the TUSB6250 pausing and terminating a UDMA read
transfer. The exact word (2-byte) count for this data is stored in the ULRCVEXCNT register.
It should be noted that the extra number of bytes received are discarded right away, because
the TUSB6250 already received the expected number of bytes. However, the TUSB6250
continues to calculate CRC for all the extra data received until the TUSB6250 terminates the
UDMA read transfer. The ATA/ATAPI device, which sent more data than expected, but
stopped sending data after the TUSB6250 terminates the UDMA read transfer, does not
receive any CRC error from the TUSB6250.
7 RSV 0 Reserved
11.6.10 SECWRPTL: Sector FIFO Write Pointer Low-Byte Register (XDATA at F0EB)
76543210
WR_PTR7 WR_PTR6 WR_PTR5 WR_PTR4 WR_PTR3 WR_PTR2 WR_PTR1 WR_PTR0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
7−0 WR_PTR[7:0] 00h This register contains the sector FIFO write pointer lower 8-bit value. Read-only