Datasheet

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ATA/ATAPI Interface Port

11−23

SLLS535E − March 2008 TUSB6250

ATP_BSY 0 ATA/ATAPI busy.

This bit, when set, indicates the ATA/ATAPI device is busy at the start of the command (after

writing START_ATAPI). The command is not executed in the autocommand mode.

The MCU must read the Task_File registers to determine why the ATA/ATAPI device is busy.

7−4 RSV 0h Reserved

11.6.9 ATPSTATUS: ATA/ATAPI Interface Status Register (XDATA at F0EA)

The ATPSTATUS register provides some status information on the ATA/ATAPI interface. Bit 0 indicates the

ATA/ATAPI device overrun condition. Bits 3–1 mirror the real-time logic level on the DMARQ, DMACK

, and

INTRQ pins.

76 5 43210

RSV ULTRARCV_EX SYNBUF_RCVERR BUFOVFLOW INTRQ DMACK DMARQ ATP_OVRUN

R/O R/O R/O R/O R/O R/O R/O R/C

BIT

NAME RESET FUNCTION

0 ATP_OVRUN 0 ATA/ATAPI device overrun.

This bit, when set, indicates that the ATA/ATAPI device attempts to process more data than

the USB host expected (dCBWDataTransferLength in the USB mass storage bulk-only

spec). This bit reflects the H < D cases defined by the Universal Serial Bus Mass Storage

Class Bulk-Only Transport specification.

 It should be noted that when ATP_OVRUN occurs, the ATP_BYTECN_MIS interrupt is

triggered. However, the transfer byte-count register may have a zero value to indicate the

TUSB6250 moved H number of bytes, as expected by the USB host.

 In the PIO auto-data transfer mode, INTRQ may be set when a device-overrun condition

occurs. If reading the ATAPI status register returns DRQ=1, the ATP_OVRUN bit is set

to reflect the condition that the device attempts to process more data than expected.

 In the DMA/UDMA auto-data transfer mode (UDMA read), when a device-overrun

condition occurs, the TUSB6250 pauses and tries to stop the current UDMA-read

transfer. The ATP_OVRUN bit is not set if INTRQ is asserted thereafter. It is set only when

INTRQ is not asserted; however DMARQ is asserted again.

This bit can be cleared by either writing a 1 to this bit or setting the START_ATAPI bit in the

ATAIFCNFG1 register.

1 DMARQ 0 DMARQ status bit.

This bit mirrors the real-time status on the DMARQ pin.

2 DMACK 0 DMACK status bit.

This bit mirrors the real-time status on the DMACK

pin.

3 INTRQ 0 INTRQ status bit.

This bit mirrors the real-time status on the INTRQ pin.