Datasheet

ATA/ATAPI Interface Port
11−22
SLLS535E − March 2008TUSB6250
2
ATP_BYTECN_MIS 0 ATA/ATAPI byte-count mismatch.
This bit, when set, indicates that there is a byte-count mismatch that occurred for the
current data transfer at the ATA/ATAPI interface. The MCU is responsible for reading the
ATA/ATAPI interface status register or transfer byte-count register to determine the actual
event causing the mismatch.
3 USB_XFR_DN 0 USB transfer done.
This bit, when set, indicates the data transfer is finished at the USB interface side, which
does not mean the transfer ended free of error. The MCU is responsible for checking
whether any byte-count mismatch occurred.
4 USB_XFR_PEND 0 USB transfer pending.
This bit, when set, indicates the data transfer at the USB interface side is not finished and
a byte-count mismatch or other error condition is pending. The MCU must check the other
registers to determine the exact error that occurred. Before clearing this interrupt, the
MCU must ensure the USBWPNABRTEN bit is set correctly, so that the state machine can
either flush or send the data in the sector FIFO to the ATAPI device.
5 ATP_XFR_DN ATA/ATAPI transfer done.
This bit, when set, indicates the data transfer is finished at the ATA/ATAPI interface side,
which does not mean the transfer ended free of error. The MCU is responsible for checking
whether any byte-count mismatch occurred.
6 ATP_ER 0 ATA/ATAPI error.
This bit, when set, indicates an error occurred during the ATA/ATAPI autocommand
sequence. The MCU must read the Taks_File registers to determine the cause of the error.
7 ATP_COMP 0 ATA/ATAPI normal completion.
This bit, when set, indicates the command execution is finished without any error.
When ATP_COMP is set, the MCU must write a 1 to clear it back to 0.
NOTES: 1. Most of the interrupt sources indicated in this register, except the ATP_INT bit, reflect the ATA interrupt with the vector
interrupt value of 0x48.
2. The interrupt sources indicated in the ATA interrupt are the most common. For other interrupt sources that happen less
frequently, the ATPINT1_PEND bit provides an easy indication to the MCU whether any of them occurred for the current
pending interrupt as indicated in the ATPINTRPT1 register.
3. The ATA interrupt mask register 0 is the interrupt enable register that can be read and written by the MCU. To enable a
particular interrupt, the MCU must write a 1 to the corresponding bit.
11.6.8 ATPINTRPT1: ATA/ATAPI Interrupt Register 1 and ATPINTMSK1: ATA/ATAPI
Interrupt Mask Register 1 (XDATA at F0E8, F0E9)
This register set includes two registers: the ATA/ATAPI interrupt register 1 (allocated at MMR address 0xF0E8)
and the ATA/ATAPI interrupt mask register 1 (allocated at MMR address 0xF0E9). See the notes in Section
11.6.7, ATPINTRPT0: ATA/ATAPI Interrupt Register 0 and ATPINTMSK0: ATA/ATAPI Interrupt Mask Register
0 (XDATA at F0E6, F0E7), for the related information.
76543 2 1 0
RSV RSV RSV RSV ATP_BSY ATP_SEQ_ER ATP_DSEQ_ER ATP_NDA_CMD
R/O R/O R/O R/O R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 ATP_NDA_CMD 0 ATA nondata command mismatch.
This bit, when set, indicates that:
 A nondata command is specified in the ATA/ATAPI interface configuration register 1.
 When the command is issued, the ATA/ATAPI device indicates the data transfer operation
is currently active.
1 ATP_DSEQ_ER 0 ATAPI data sequence error.
In the ATAPI mode, this bit indicates there is a sequence error that occurred during data
transfer. The MCU must read the interrupt reason register and byte-count register (both in the
storage device) to determine the cause of the error.
2 ATP_SEQ_ER 0 ATAPI sequence error.
In the ATAPI mode with full autosequencing, this bit indicates that a sequence error has
occurred after writing a packet command (command code A0h), but before the command
packet bytes have been issued.
The MCU must read the ATAPI interrupt reason register to determine the cause of the error.