Datasheet

ATA/ATAPI Interface Port
11−21
SLLS535E − March 2008 TUSB6250
11.6.5 MCUACSL: MCU Access Address Low-Byte Register (XDATA at F0E4)
76543210
MACS_ADR7 MACS_ADR6 MACS_ADR5 MACS_ADR4 MACS_ADR3 MACS_ADR2 MACS_ADR1 MACS_ADR0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 MACS_ADR[7:0] 00h MCU access address[7:0]. These bits contain the MCU access sector FIFO memory address
lower 8 bits.
11.6.6 MCUACSH: MCU Access Address High-Byte Register (XDATA at F0E5)
7 6 5 4 3 2 1 0
MACS_DIR MACS_BUSY RSV MACS_ADR12 MACS_ADR11 MACS_ADR10 MACS_ADR9 MACS_ADR8
R/W R/O R/O R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
4−0 MACS_ADR[12:8] 00000 MCU access address[12:8]. These bits contain the MCU access sector FIFO
memory address higher 5 bits.
5 RSV 0 Reserved
6 MACS_BUSY 0 MCU access busy. Read-only.
This bit, when set, indicates the internal logic is busy prefetching the next 32-bit
read data or writing the 32-bit data to the sector FIFO memory from the MCU data
byte 0−3 registers.
7 MACS_DIR 0 MCU access direction.
 If MACS_DIR = 0, MCU is going to write data to sector FIFO memory.
 If MACS_DIR = 1, MCU is going to read data from sector FIFO memory.
When the MCU sets MACS_DIR to 1 by first writing to the MCU access address
high-byte register, the internal logic prefetches the read data pointed by
MACS_ADR[12:0], stores the read data in the MCU data byte 0−3 registers, and
increments MACS_ADR[12:0] by 1.
11.6.7 ATPINTRPT0: ATA/ATAPI Interrupt Register 0 and ATPINTMSK0: ATA/ATAPI
Interrupt Mask Register 0 (XDATA at F0E6, F0E7)
This register set includes the ATA/ATAPI interrupt register 0 (allocated at the MMR address 0xF0E6) and the
ATA/ATAPI interrupt mask register 0 (allocated at the MMR address 0xF0E7).
The ATA/ATAPI interrupt register 0 provides the source information of the interrupt. The MCU can read this
register to determine the source of a pending interrupt, if any. To clear a particular interrupt, the MCU must
write a 1 to the corresponding bit to clear it to 0. There is another way to clear the USB_XFR_DN and
ATP_XFR_DN interrupts, which is automatically cleared to 0 when the firmware sets the START_ATAPI bit
in the ATPIFCNFG1 register to begin a data transfer.
7 6 5 4 3 2 1 0
ATP_COMP ATP_ER ATP_XFR_DN USB_XFR_PEND USB_XFR_DN ATP_BYTECN_MIS ATPINT1_PEND ATP_INT
R/W R/W R/W R/W R/W R/W R/O R/W
BIT
NAME RESET FUNCTION
0 ATP_INT 0 ATAPI interrupt. This bit indicates that an interrupt has occurred at the ATA/ATAPI
interface.
 ATP_INT is set only during the manual phase of a sequence.
 During the automatic phase of a sequence, the hardware handles ATA INTRQ
automatically without the MCU intervention.
1 ATPINT1_PEND 0 Interrupt pending in ATPINTRPT1.
This bit, when set, indicates that in addition to the interrupt source indicated in this register
(ATPINTRPT0), there is also some other interrupt source for the current pending ATA
interrupt (vector value = 0x48) reflected in the vector interrupt register.