Datasheet

ATA/ATAPI Interface Port
11−20
SLLS535E − March 2008TUSB6250
MACS_BUSY to 1. When the internal logic reads from the sector FIFO memory, it loads the 32-bit data
into the MCU data Byte_3 register (MCUBYTE3), MCU data Byte_2 register (MCUBYTE2), MCU data
Byte_1 register (MCUBYTE1), MCU data Byte_0 register (MCUBYTE0), clears MACS_BUSY to 0, and
increments MACS_ADR[12:0] by 1.
3. The MCU reads the MCU data Byte_0 register (MCUBYTE0), MCU data Byte_1 register (MCUBYTE1),
MCU data Byte_2 register (MCUBYTE2), and the MCU data Byte_3 register (MCUBYTE3) in this fixed
order.
4. After the MCU finishes the read from the MCU data Byte_3 register, the internal logic prefetches the next
32-bit data from sector FIFO pointed to by the current MACS_ADR[12:0]. The same sequence as
described in Steps 2 and 3 is followed for consecutive reads until the MCU writes to the MCU access
address register with a new address.
5. Noted that although the MCU is allowed to read part of the 32-bit read data, it must ensure that the last
read goes to the MCU data Byte_3 register (MCUBYTE3). This serves as an indication to the TUSB6250
internal logic that the MCU has finished the read process to the current 32-bit read data and is ready to
let the internal logic fetch the next 32-bit data. Without the read from the MCUBYTE3 register, the internal
logic does not perform prefetch of the next 32-bit data.
11.6.1 MCUBYTE0: MCU Data Byte_0 Register (XDATA at F0E0)
76543210
MACS_DB07 MACS_DB06 MACS_DB05 MACS_DB04 MACS_DB03 MACS_DB02 MACS_DB01 MACS_DB00
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 MACS_DB0[7:0] 00h This register contains the sector FIFO memory data buffer byte 0 accessible by the MCU.
11.6.2 MCUBYTE1: MCU Data Byte_1 Register (XDATA at F0E1)
76543210
MACS_DB17 MACS_DB16 MACS_DB15 MACS_DB14 MACS_DB13 MACS_DB12 MACS_DB11 MACS_DB10
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 MACS_DB1[7:0] 00h This register contains the sector FIFO memory data buffer byte 1 accessible by the MCU.
11.6.3 MCUBYTE2: MCU Data Byte_2 Register (XDATA at F0E2)
76543210
MACS_DB27 MACS_DB26 MACS_DB25 MACS_DB24 MACS_DB23 MACS_DB22 MACS_DB21 MACS_DB20
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 MACS_DB2[7:0] 00h This register contains the sector FIFO memory data buffer byte 2 accessible by the MCU.
11.6.4 MCUBYTE3: MCU Data Byte_3 Register (XDATA at F0E3)
76543210
MACS_DB37 MACS_DB36 MACS_DB35 MACS_DB34 MACS_DB33 MACS_DB32 MACS_DB31 MACS_DB30
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 MACS_DB3[7:0] 00h This register contains the sector FIFO memory data buffer byte 3 accessible by the MCU.