Datasheet

ATA/ATAPI Interface Port
11−19
SLLS535E − March 2008 TUSB6250
11.6 ATA/ATAPI Group 2 Registers
Table 11−7. Group 2 Registers
MMR ADDRESS
OFFSET ADDRESS
(BASE ADDRESS = F0C0)
REGISTER DESCRIPTION
F0E0 20h MCU data Byte_0 register
F0E1 21h MCU data Byte_1 register
F0E2 22h MCU data Byte_2 register
F0E3 23h MCU data Byte_3 register
F0E4 24h MCU access address low-byte register
F0E5 25h MCU access address high-byte register
F0E6 26h ATA/ATAPI interrupt register 0
F0E7 27h ATA/ATAPI interrupt mask register 0
F0E8 28h ATA/ATAPI interrupt register 1
F0E9 29h ATA/ATAPI interrupt mask register 1
F0EA 2Ah ATA/ATAPI interface status register
F0EB 2Bh Sector FIFO write pointer low-byte register
F0EC 2Ch Sector FIFO write pointer high-byte register
F0ED 2Dh Sector FIFO write pointer backup low-byte register
F0EE 2Eh Sector FIFO write pointer backup high-byte register
F0EF 2Fh Sector FIFO read pointer low-byte register
F0F0 30h Sector FIFO read pointer high-byte register
F0F1 31h Sector FIFO read pointer backup low-byte register
F0F2 32h Sector FIFO read pointer backup high-byte register
F0F9 39h Ultra receive extra word count
The MCU can access the sector FIFO memory indirectly by using the MCU access address low/high registers
(MCUACSL and MCUACSH) and the MCU data registers (MCUBYTE[0:3]). The access address and direction
must be set before the data access can occur. The write and read sequences are described in detail as follows.
MCU Write to Sector FIFO Memory:
1. The MCU writes to the MCU access address low-byte register (MCUACSL), then to the MCU access
address high-byte register (MCUACSH) to set up the start address in MACS_ADR[12:0], and set
MACS_DIR to 0.
2. The MCU writes to the MCU data Byte_0 register (MCUBYTE0), MCU data Byte_1 register (MCUBYTE1),
MCU data Byte_2 register (MCUBYTE2), MCU data Byte_3 register (MCUBYTE3), in this fixed order.
After the MCU finishes the write to the MCU data Byte_3 register (MCUBYTE3), the internal logic writes
the complete 32-bit data into the sector FIFO location with the address pointed to by MACS_ADR[12:0]
and sets MACS_BUSY to 1.
3. After the internal logic finishes the write of 32-bit data into sector FIFO, it clears MACS_BUSY to 0, and
increments MACS_ADR[12:0] by 1.
4. The MCU continues steps 2 and 3 to write the next 32-bit data into sector FIFO for consecutive writes,
until the MCU writes to the MCU access address register with a new address.
MCU Read to Sector FIFO Memory:
1. The MCU writes to the MCU access address low-byte register (MCUACSL) and then to the MCU access
address high-byte register (MCUACSH) to set up the start address in MACS_ADR[12:0] and set
MACS_DIR to 1.
2. After the MCU finishes the write to the MCU access address high-byte register (MCUACSH), the internal
logic prefetches the 32-bit data from sector FIFO memory pointed to by MACS_ADR[12:0] and sets