Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller (user-defined) TUSB3410 USB serial port controller LQFP 32

UART

SLLS519H—January 2010TUSB3410, TUSB3410I

7.1.13 XOFF: Xoff Register (Addr:FFAAh)

This register contains a value that is compared to the received data stream. Detection of a match halts the

DMA transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff

transmission.

765 4 32 1 0

D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT

NAME RESET FUNCTION

7−0 D[7:0] 0000 Xoff value to be compared to the incoming data stream

7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFABh)

This register controls the UARTs interrupt sources.

765 4 32 1 0

RSV RSV RSV RSV RSV TRI SIE MIE

R/O R/O R/O R/O R/O R/W R/W R/W

BIT

NAME RESET FUNCTION

0 MIE 0

This bit controls the UART-modem interrupt.

MIE = 0

MIE = 1

Modem interrupt is disabled

Modem interrupt is enabled

1 SIE 0

This bit controls the UART-status interrupt.

SIE = 0

SIE = 1

Status interrupt is disabled

Status interrupt is enabled

2 TRI 0

This bit controls the UART-TxE/RxF interrupts

TRI = 0

TRI = 1

TxE/RxF interrupts are disabled

TxE/RxF interrupts are enabled

7−3 RSV 0 Reserved = 0

7.2 UART Data Transfer

Figure 7−2 illustrates the data transfer between the UART and the host using the DMA controller and the USB

buffer manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit and receive

buffers). The UART channel has 64 bytes of double-buffer space (X- and Y-buffer). When the DMA writes to

the X-buffer, the UBM reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes

to the Y-buffer. The DMA channel is configured to operate in the continuous mode (by setting bit 5 (CNT) in

the DMACDR registers = 1). Once the MCU enables the DMA, data transfer toggles between the UMB and

the DMA without MCU intervention. See Section 6.2.1, IN Transaction (TUSB3410 to Host), for DMA

transfer-termination condition.

7.2.1 Receiver Data Flow

The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark

(HALT), which is set to 12 bytes, and the other is the low-level mark (RESUME), which is set to 4 bytes. When

the HALT mark is reached, either the RTS

terminal goes high or Xoff is transmitted (depending on the auto

setting). When the FIFO reaches the RESUME mark, then either the RTS

terminal goes low or Xon is

transmitted.