Datasheet

UART
46
SLLS519H—January 2010TUSB3410, TUSB3410I
7.1.8 MSR: Modem-Status Register (Addr:FFA6h)
This register provides information about the current state of the control lines from the modem.
765 4 32 1 0
LCD LRI LDSR LCTS ΔCD TRI ΔDSR ΔCTS
R/O R/O R/O R/O R/C R/C R/C R/C
BIT NAME RESET FUNCTION
0 ΔCTS 0 This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a
0 has no effect.
1 ΔDSR 0
This bit indicates that the DSR input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a
0 has no effect.
ΔDSR = 0
ΔDSR = 1
Indicates no change in the DSR input
Indicates that the DSR
input has changed state since the last time it was read. Clears when the MCU
writes a 1. Writing a 0 has no effect.
2 TRI 0
Trailing edge of the ring indicator. This bit indicates that the RI/CP input has changed from low to high. This bit
is cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect.
TRI = 0
TRI = 1
Indicates no applicable transition on the RI/CP input
Indicates that an applicable transition has occurred on the RI
/CP input.
3 ΔCD 0
This bit indicates that the CD input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0
has no effect.
ΔCD = 0
ΔCD = 1
Indicates no change in the CD input
Indicates that the CD
input has changed state since the last time it was read.
4 LCTS 0
During loopback, this bit reflects the status of bit 4 (DTR) in the MCR register, see Section 7.1.6 (see
Figure 7−1)
LCTS = 0
LCTS = 1
CTS input is high
CTS
input is low
5 LDSR 0
During loop back, this bit reflects the status of bit 5 (RTS) in the MCR register, see Section 7.1.6 (see
Figure 7−1)
LDSR = 0
LDSR= 1
DSR input is high
DSR
input is low
6 LRI 0
During loop back, this bit reflects the status of bit 6 (LRI) in the MCR register, see Section 7.1.6 (see
Figure 7−1)
LRI = 0
LRI = 1
RI/CP input is high
RI
/CP input is low
7 LCD 0
During loopback, this bit reflects the status of bit 7 (LCD) in the MCR register, see Section 7.1.6 (see
Figure 7−1)
LCD = 0
LCD = 0
CD input is high
CD
input is low
7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7h)
This register contains the low byte of the baud-rate divisor.
765 4 32 1 0
D7
D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 D[7:0] 08h Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.