Datasheet

UART
40
SLLS519H—January 2010TUSB3410, TUSB3410I
7.1.3 LCR: Line Control Register (Addr:FFA2h)
This register controls the data communication format. The word length, number of stop bits, and parity type
are selected by writing the appropriate bits to the LCR.
765 4 32 1 0
FEN BRK FPTY EPRTY PRTY STP WL1 WL0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
1:0 WL[1:0] 0 Specifies the word length for transmit and receive
00b = 5 bits
01b = 6 bits
10b = 7 bits
11b = 8 bits
2 STP 0
Specifies the number of stop bits for transmit and receive
STP = 0
STP = 1
STP = 1
1 stop bit (word length = 5, 6, 7, 8)
1.5 stop bits (word length = 5)
2 stop bits (word length = 6, 7, 8)
3 PRTY 0
Specifies whether parity is used
PRTY = 0
PRTY = 1
No parity
Parity is generated
4 EPRTY 0
Specifies whether even or odd parity is generated
EPRTY = 0
EPRTY = 1
Odd parity is generated (if bit 3 (PRTY) = 1)
Even parity is generated (if PRTY = 1)
5 FPTY 0
Selects the forced parity bit
FPTY = 0
FPTY = 1
Parity is not forced
Parity bit is forced. If bit 4 (EPRTY) = 0, the parity bit is forced to 1
6 BRK 0
This bit is the break-control bit
BRK = 0
BRK = 1
Normal operation
Forces SOUT into break condition (logic 0)
7 FEN 0
FIFO enable. This bit disables/enables the FIFO. To reset the FIFO, the MCU clears and then sets this bit.
FEN = 0
FEN = 1
The FIFO is cleared and disabled. When disabled, the selected receiver flow control is activated.
The FIFO is enabled and it can receive data.