Datasheet

DMA Controller

SLLS519H—January 2010TUSB3410, TUSB3410I

6.2.2 OUT Transaction (Host to TUSB3410)

1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

• DMACSR1: Provides an indication of a partial packet.

• DMACDR1: Defines the output endpoint being used, and the DMA mode of operation (continuous

mode). Once the EN bit is set to 1 in this register, the transfer starts.

2. The UBM transfers data from host to X-buffer. When a block of 64 bytes is transferred, the UBM updates

the byte count and sets NAK to 1 in the output endpoint byte count register (indicating to DMA that the

X-buffer is ready to be transferred to the UART). The DMA starts X-buffer transfer using the byte-count

value in the output endpoint byte count register. The UBM continues transferring data from host to Y-buffer.

At the end of the block transfer, the UBM updates the byte count and sets NAK to 1 in the output endpoint

byte count register (indicating to DMA that the Y-buffer is ready to be transferred to device). The DMA

continues the transfer from the X-/Y-buffers to the device, alternating between X- and Y-buffers without

MCU intervention.

3. Transfer termination: The DMA/UBM continues the data transfer alternating between X- and Y-buffers.

The termination of the transfer can happen under the following conditions:

• Stop Transfer: The host notifies the MCU (via control-end point) to stop the transfer. Under this

condition, the MCU sets EN to 0 in the DMACDR1 register.

• Partial-Packet: UBM receives a partial packet from host. Under this condition, the byte-count value is

less than 64. When the DMA detects this condition, it transfers the partial packet to the device, sets

PPKT to 1, updates NAK to 0 in the output endpoint byte count register, and interrupts the MCU.