Datasheet

DMA Controller

SLLS519H—January 2010 TUSB3410, TUSB3410I

6 DMA Controller

Table 6−1 outlines the DMA channels and their associated transfer directions. Two channels are provided for

data transfer between the host and the UART.

Table 6−1. DMA Controller Registers

DMA CHANNEL TRANSFER DIRECTION COMMENTS

DMA−1 Host to UART DMA writes to UART TDR register

DMA−3 UART to host DMA reads from UART RDR register

6.1 DMA Controller Registers

Each DMA channel can point to one of three EDBs (EDB-1 to EDB-3) and transfer data to/from the UART

channel. The DMA can move data from a given out-point buffer (defined by the EDB) to the destination port.

Similarly, the DMA can move data from a port to a given input-endpoint buffer.

At the end of a block transfer, the DMA updates the byte count and bit 7 (NAK) in the EDB (see Section 4.3)

when receiving. In addition, it uses bit 4 (XY) in the DMACDR register to switch automatically, without

interrupting the MCU (the XY bit toggle is performed by the UBM). The DMA stops only when a time-out or

error condition occurs. When the DMA is transmitting (from the X/Y buffer) it continues alternating between

X/Y buffers until it detects a byte count smaller than the buffer size (buffer size is typically 64 bytes). At that

point it completes the transfer and stops.