Datasheet

MCU Memory Map
14
SLLS519H—January 2010TUSB3410, TUSB3410I
4.1 Miscellaneous Registers
4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)
This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on
power-on reset only). In addition, this register provides the device revision number and the ROM/RAM
configuration.
765 4 32 1 0
ROA
S1 S0 RSVD RSVD RSVD RSVD SDW
R/O R/O R/O R/O R/O R/O R/O R/W
BIT
NAME RESET FUNCTION
0 SDW 0
This bit enables/disables boot ROM. (Shadow the ROM).
SDW = 0 When clear, the MCU executes from the 10K boot ROM space. The boot ROM appears in two
locations: 0000h and 8000h. The 16K RAM is mapped to XDATA space; therefore, a read/write
operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU
cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset.
SDW = 1 When set by the MCU, the 10K boot ROM maps to location 8000h, and the 16K RAM is mapped
to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the
write operation is disabled (no write operation is possible in code space).
4−1 RSVD No effect These bits are always read as 0000b.
6−5 S[1:0] No effect Code space size. These bits define the ROM or RAM code-space size (bit 7 (ROA) defines ROM or
RAM). These bits are permanently set to 10b, indicating 16K bytes of code space, and are not affected
by reset (see Table 4−1).
00 = 4K bytes code space size
01 = 8K bytes code space size
10 = 16K bytes code space size
11 = 32K bytes code space size
7 ROA No effect ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is
permanently set to 1, indicating the code space is RAM, and is not affected by reset (see Table 4−1).
ROA = 0 Code space is ROM
ROA = 1 Code space is RAM
Table 4−1. ROM/RAM Size Definition Table
ROMS REGISTER
BOOT ROM
RAM CODE
ROM CODE
ROA S1 S0
BOOT ROM RAM CODE ROM CODE
0 0 0 None None 4K
0 0 1 None None 8K
0 1 0 None None 16K (reserved)
1 1 1 None None 32K (reserved)
1 0 0 10K 4K None
1 0 1 10K 8K None
1
†
1
†
0
†
10K
†
16K
†
None
†
1 1 1 10K 32K (reserved) None
†
This is the hardwired setting.
4.1.2 Boot Operation (MCU Firmware Loading)
Since the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must be loaded
from an external source. Two sources are available for booting: one from an external serial EEPROM
connected to the I
2
C bus and the other from the host via the USB. On device reset, bit 0 (SDW) in the ROMS
register (see Section 4.1.1) and bit 7 (CONT) in the USBCTL register (see Section 5.4) are cleared. This
configures the memory space to boot mode (see Table 4−3) and keeps the device disconnected from the host.
The first instruction is fetched from location 0000h (which is in the 10K ROM). The 16K RAM is mapped to
XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests whether it
contains the code (by testing for boot signature). If it contains the code, then the MCU reads from EEPROM