Datasheet

Main Features
7
SLLS519H—January 2010 TUSB3410, TUSB3410I
Table 2−1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CLKOUT 22 O Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see
Section 5.5 and Note 1)
CTS 13 I UART: Clear to send (see Note 4)
DCD 15 I UART: Data carrier detect (see Note 4)
DM 7 I/O Upstream USB port differential data minus
DP 6 I/O Upstream USB port differential data plus
DSR 14 I UART: Data set ready (see Note 4)
DTR 21 O UART: Data terminal ready (see Note 1)
GND 8, 18, 28 GND Digital ground
P3.0 32 I/O General-purpose I/O 0 (port 3, terminal 0) (see Notes 3, 5, and 8)
P3.1 31 I/O General-purpose I/O 1 (port 3, terminal 1) (see Notes 3, 5, and 8)
P3.3 30 I/O General-purpose I/O 3 (port 3, terminal 3) (see Notes 3, 5, and 8)
P3.4 29 I/O General-purpose I/O 4 (port 3, terminal 4) (see Notes 3, 5, and 8)
PUR 5 O Pull-up resistor connection (see Note 2)
RESET 9 I Device master reset input (see Note 4)
RI/CP 16 I UART: Ring indicator (see Note 4)
RTS 20 O UART: Request to send (see Note 1)
SCL 11 O Master I
2
C controller: clock signal (see Note 1)
SDA 10 I/O Master I
2
C controller: data signal (see Notes 1 and 5)
SIN/IR_SIN 17 I UART: Serial input data / IR Serial data input (see Note 6)
SOUT/IR_SOUT 19 O UART: Serial output data / IR Serial data output (see Note 7)
SUSPEND 2 O Suspend indicator terminal (see Note 3). When this terminal is asserted high, the device is in
suspend mode.
TEST0 23 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ
resistor.
TEST1 24 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ
resistor.
VCC 3, 25 PWR 3.3 V
VDD18 4 PWR 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is
low. When VREGEN
is high, 1.8 V must be supplied externally.
VREGEN 1 I This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator.
WAKEUP 12 I Remote wake-up request terminal. When low, wakes up system (see Note 5)
X1/CLKI 27 I 12-MHz crystal input or clock input
X2 26 O 12-MHz crystal output
NOTES: 1. 3-state CMOS output (±4-mA drive/sink)
2. 3-state CMOS output (±8-mA drive/sink)
3. 3-state CMOS output (±12-mA drive/sink)
4. TTL-compatible, hysteresis input
5. TTL-compatible, hysteresis input, with internal 100-μA active pullup resistor
6. TTL-compatible input without hysteresis, with internal 100-μA active pullup resistor
7. Normal or IR mode: 3-state CMOS output (±4-mA drive/sink)
8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two
clock cycles and then the output is high impedance.