Datasheet

Application Notes
82
SLLS519H—January 2010TUSB3410, TUSB3410I
13.3 Wakeup Timing (WAKEUP or RI/CP Transitions)
The TUSB3410 can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410
also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP
terminal or a low-to-high transition on the RI/CP terminal wakes the device up. Note that for reliable operation, either
condition must persist for approximately 3 ms minimum. This allows time for the crystal to power up since in the
suspend mode the crystal interface is powered down. The state of the WAKEUP
or RI/CP terminal is then sampled
by the clock to verify there was a valid wakeup event.
13.4 Reset Timing
There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs. At power
up, this time is measured from the time the power ramps up to 90% of the nominal V
CC
until the reset signal exceeds
1.2 V. The second requirement is that the clock must be valid during the last 60 μs of the reset window. The third
requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms.
This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I
2
C
EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events
can require significant time, the amount of which can change from system to system, TI recommends having the
device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal
must rise to 1.8 V within 30 ms.
These requirements are depicted in Figure 13−3. Notice that when using a 12-MHz crystal, the clock signal may take
several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be
elongated up to 10 ms or more to ensure that there is a 60-μs overlap with a valid clock.
CLK
RESET
t
V
CC
90%
3.3 V
1.2 V
0 V
>60 μs
100 μs < RESET TIME
1.8 V
RESET TIME < 30 ms
Figure 13−3. Reset Timing