Datasheet

I
2
C Port
59
SLLS519H—January 2010 TUSB3410, TUSB3410I
• The contents of the I2CDAO register are transmitted to EEPROM (EPROM address).
• Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has
been transmitted.
• A stop condition is not generated.
EPROM [Low Byte]
• The MCU writes the low byte of the EEPROM address into the I2CDAO register.
• Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO
register.
• The contents of the I2CDAO register are transmitted to the device (EEPROM address).
• Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has
been transmitted.
• This completes the dummy write operation. At this point, the EEPROM address is set and the MCU can
do either a single- or a sequential-read operation.
10.3 Current-Address Read Operation
Once the EEPROM address is set, the MCU can read a single byte by executing the following steps:
• The MCU sets bit 1 (SRD) in the I2CSTA register to 1. This forces the I
2
C controller to generate a stop
condition after the I2CDAI-register contents are received.
• The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).
• The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line).
• Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).
• The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA).
• The data from EEPROM are latched into the I2CDAI register (stop condition is transmitted).
• Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that the data are available.
• The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
10.4 Sequential-Read Operation
Once the EEPROM address is set, the MCU can execute a sequential read operation by executing the
following (this example illustrates a 32-byte sequential read):
Device Address
• The MCU clears bit 1 (SRD) in the I2CSTA register. This forces the I
2
C controller to not generate a stop
condition after the I2CDAI register contents are received.
• The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).
• The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on the SDA line).
• Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).
• The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).