Datasheet
I
2
C Port
58
SLLS519H—January 2010TUSB3410, TUSB3410I
10.1.2 I2CADR: I
2
C Address Register (Addr:FFF3h)
This register holds the device address and the read/write command bit.
765 4 32 1 0
A6 A5 A4 A3 A2 A1 A0 R/W
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 R/W 0
Read/write command bit
R/W = 0
R/W = 1
Write operation
Read operation
7−1 A[6:0] 0h Seven address bits for device addressing
10.1.3 I2CDAI: I
2
C Data-Input Register (Addr:FFF2h)
This register holds the received data from an external device.
765 4 32 1 0
D7
D6 D5 D4 D3 D2 D1 D0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
7−0 D[7:0] 0 8-bit input data from an I
2
C device
10.1.4 I2CDAO: I
2
C Data-Output Register (Addr:FFF1h)
This register holds the data to be transmitted to an external device. Writing to this register starts the transfer
on the SDA line.
765 4 32 1 0
D7
D6 D5 D4 D3 D2 D1 D0
W/O W/O W/O W/O W/O W/O W/O W/O
BIT
NAME RESET FUNCTION
7−0 D[7:0] 0 8-bit output data to an I
2
C device
10.2 Random-Read Operation
A random read requires a dummy byte-write sequence to load in the data word address. Once the
device-address word and the data-word address are clocked out and acknowledged by the device, the MCU
starts a current-address sequence. The following describes the sequence of events to accomplish this
transaction.
Device Address + EPROM [High Byte]
• The MCU clears bit 1 (SRD) within the I2CSTA register. This forces the I
2
C controller not to generate a
stop condition after the contents of the I2CDAI register are received.
• The MCU clears bit 0 (SWR) within the I2CSTA register. This forces the I
2
C controller not to generate a
stop condition after the contents of the I2CDAO register are transmitted.
• The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation)
• The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the transfer
on the SDA line).
• Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing data to the I2CDAO
register.
• The contents of the I2CADR register are transmitted to EEPROM (preceded by start condition on SDA).