Datasheet

UART
44
SLLS519H—January 2010TUSB3410, TUSB3410I
7.1.7 LSR: Line-Status Register (Addr:FFA5h)
This register provides the status of the data transfer. DMA transfer is halted when any of bit 0 (OVR), bit 1
(PTE), bit 2 (FRE), or bit 3 (BRK) is 1.
765 4 32 1 0
RSV TEMT TxE RxF BRK FRE PTE OVR
R/O R/O R/O R/O R/C R/C R/C R/C
BIT
NAME RESET FUNCTION
0 OVR 0
This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a
status interrupt (if enabled).
OVR = 0
OVR = 1
No overrun error
Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.
1 PTE 0
This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a
status interrupt (if enabled).
PTE = 0
PTE = 1
No parity error in data received
Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.
2 FRE 0
This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates
a status interrupt (if enabled).
FRE = 0
FRE = 1
No framing error in data received
Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.
3 BRK 0
This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a
status interrupt (if enabled).
BRK = 0
BRK = 1
No break condition
A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0
has no effect.
4 RxF 0
This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit
since data transfer is done by the DMA controller.
RxF = 0
RxF = 1
No data in the RDR
RDR contains data. Generates Rx interrupt (if enabled).
5 TxE 1
This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit
since data transfer is done by the DMA controller.
TxE = 0
TxE = 1
TDR is not empty
TDR is empty. Generates Tx interrupt (if enabled).
6 TEMT 1
This bit indicates the condition of both transmitter data register and shift register is empty.
TEMT = 0
TEMT = 1
Either TDR or TSR is not empty
Both TDR and TSR are empty
7 RSV 0 Reserved = 0