Datasheet

UART
43
SLLS519H—January 2010 TUSB3410, TUSB3410I
7.1.6 MCR: Modem-Control Register (Addr:FFA4h)
This register provides control for modem interface I/O and definition of the flow control mode.
765 4 32 1 0
LCD
LRI RTS DTR RSV LOOP RCVE URST
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0 URST 0
UART soft reset. This bit can be used by the MCU to reset the UART.
URST = 0 Normal operation. Writing a 0 by MCU has no effect.
URST = 1 When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When
the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the
UART completed the reset cycle.
1 RCVE 0
Receiver enable bit. This bit is valid only when bit 7 (485E) in the FCRL register (see Section 7.1.4) is 1 (RS-485
mode). When 485E = 0, this bit has no effect on the receiver.
RCVE = 0 When 485E = 1, the UART receiver is disabled when RTS = 1, i.e., when data is being transmitted,
the UART receiver is disabled.
RCVE = 1 When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver
is enabled all the time. This mode can detect collisions on the RS-485 bus when received data
does not match transmitted data.
2 LOOP 0
This bit controls the normal-/loop-back mode of operation (see Figure 7−1).
LOOP = 0 Normal operation
LOOP = 1 Enable loop-back mode of operation. In this mode the following occur:
S SOUT is set high
S SIN is disconnected from the receiver input.
S The transmitter serial output is looped back into the receiver serial input.
S The four modem-control inputs: CTS
, DSR, DCD, and RI/CP are disconnected.
S DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read
in the MSR register (see Section 7.1.8) as described below. Note: the FCRL register (see
Section 7.1.4) must be configured to enable bits 2 (CTS) and 3 (DSR) to maintain proper
operation with flow control and loop back.
S DTR is reflected in MSR register bit 4 (LCTS)
S RTS is reflected in MSR register bit 5 (LDSR)
S LRI is reflected in MSR register bit 6 (LRI)
S LCD is reflected in MSR register bit 7 (LCD)
3 RSV 0 Reserved
4 DTR 0
This bit controls the state of the DTR output terminal (see Figure 7−1). This bit has no effect when auto-flow
control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4).
DTR = 0 Forces the DTR output terminal to inactive (high)
DTR = 1 Forces the DTR output terminal to active (low)
5 RTS 0
This bit controls the state of the RTS output terminal (see Figure 7−1). This bit has no effect when auto-flow
control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4).
RTS = 0 Forces the RTS output terminal to inactive (high)
RTS = 1 Forces the RTS output terminal to active (low)
6 LRI 0
This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 6 (LRI) in the MSR
register, see Section 7.1.8 (see Figure 7−1).
LRI = 0 Clears the MSR register bit 6 to 0
LRI = 1 Sets the MSR register bit 6 to 1
7 LCD 0
This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 7 (LCD) in the MSR
register, see Section 7.1.8 (see Figure 7−1).
LCD = 0 Clears the MSR register bit 7 to 0
LCD = 1 Sets the MSR register bit 7 to 1