Datasheet

UART

SLLS519H—January 2010 TUSB3410, TUSB3410I

7 UART

7.1 UART Registers

Table 7−1 summarizes the UART registers. These registers are used for data I/O, control, and status

information. UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However,

the MCU can perform data transfer without a DMA; this is useful when debugging the firmware.

Table 7−1. UART Registers Summary

FFA0h RDR R/O UART receiver data register Can be accessed by MCU or DMA

FFA1h TDR W/O UART transmitter data register Can be accessed by MCU or DMA

FFA2h LCR R/W UART line control register

FFA3h FCRL R/W UART flow control register

FFA4h MCR R/W UART modem control register

FFA5h LSR R/O UART line status register Can generate an interrupt

FFA6h MSR R/O UART modem status register Can generate an interrupt

FFA7h DLL R/W UART divisor register (low byte)

FFA8h DLH R/W UART divisor register (high byte)

FFA9h XON R/W UART Xon register

FFAAh XOFF R/W UART Xoff register

FFABh MASK R/W UART interrupt mask register Can control three interrupt sources

7.1.1 RDR: Receiver Data Register (Addr:FFA0h)

The receiver data register consists of a 32-byte FIFO. Data received via the SIN terminal is converted from

serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the

responsibility of the DMA controller.

765 4 32 1 0

D6 D5 D4 D3 D2 D1 D0

R/O R/O R/O R/O R/O R/O R/O R/O

BIT

NAME RESET FUNCTION

7−0 D[7:0] 0 Receiver byte

7.1.2 TDR: Transmitter Data Register (Addr:FFA1h)

The transmitter data register is double buffered. Data written to this register is loaded into the shift register,

and shifted out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of the DMA

controller.

765 4 32 1 0

D6 D5 D4 D3 D2 D1 D0

W/O W/O W/O W/O W/O W/O W/O W/O

BIT

NAME RESET FUNCTION

7−0 D[7:0] 0 Transmit byte