Datasheet

DMA Controller
37
SLLS519H—January 2010 TUSB3410, TUSB3410I
6.2.1 IN Transaction (TUSB3410 to Host)
1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA
registers:
• DMACSR3: Defines the transaction time-out value.
• DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once
this register is set with EN = 1, the transfer starts.
2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the DMA
updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM
that the X buffer is ready to be transferred to host). The UBM starts X-buffer transfer to host using the
byte-count value in the input endpoint byte count register and toggles the X/Y bit. The DMA continues
transferring data from a device to Y-buffer. At the end of the block transfer, the DMA updates the byte count
and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that the Y-buffer is ready
to be transferred to host). The DMA continues the transfer from the device to host, alternating between
X-and Y-buffers without MCU intervention.
3. Transfer termination: As mentioned, the DMA/UBM continues the data transfer, alternating between the
X- and Y-buffers. Termination of the transfer can happen under the following conditions:
• Stop Transfer: The host notifies the MCU (via control-end-point) to stop the transfer. Under this
condition, the MCU sets bit 7 (EN) to 0 in the DMACDR register.
• Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the
byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects
this condition, it sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, updates the
byte count and NAK bit in the the input endpoint byte count register, and interrupts the MCU. The UBM
transfers the partial packet to host.
• Buffer Overrun: The host is busy, X- and Y-buffers are full (X-NAK = 0 and Y-NAK = 0), and the DMA
cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets bit 1
(TXFT) to 1 and bit 0 (OVRUN) to 1 in the DMACSR3 register, and interrupts the MCU.
• UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA and
sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, but the EN bit remains set at 1.
Therefore, the DMA does not interrupt the MCU. However, the UART generates a status interrupt,
notifying the MCU that an error condition has occurred.