Datasheet

MCU Memory Map

SLLS519H—January 2010TUSB3410, TUSB3410I

Table 4−4. EDB Memory Locations (Continued)

ADDRESS REGISTER DESCRIPTION

FF1Ah OEPBCTX_3 Output endpoint_3: X-byte count

FF19h OEPBBAX_3 Output endpoint_3: X-buffer base address

FF18h OEPCNF_3 Output endpoint_3: Configuration

FF17h OEPSIZXY_2 Output endpoint_2: X-Y buffer size

FF16h OEPBCTY_2 Output endpoint_2: Y-byte count

FF15h OEPBBAY_2 Output endpoint_2: Y-buffer base address

FF14h−FF13h − Reserved

FF12h OEPBCTX_2 Output endpoint_2: X-byte count

FF11h OEPBBAX_2 Output endpoint_2: X-buffer base address

FF10h OEPCNF_2 Output endpoint_2: Configuration

FF0Fh OEPSIZXY_1 Output endpoint_1: X-Y buffer size

FF0Eh OEPBCTY_1 Output endpoint_1: Y-byte count

FF0Dh OEPBBAY_1 Output endpoint_1: Y-buffer base address

FF0Ch−FF0Bh − Reserved

FF0Ah OEPBCTX_1 Output endpoint_1: X-byte count

FF09h OEPBBAX_1 Output endpoint_1: X-buffer base address

FF08h OEPCNF_1 Output endpoint_1: Configuration

FF07h

↑ (8 bytes) Setup packet block

FF00h

FEFFh

↑ (8 bytes) Input endpoint_0 buffer

FEF8h

FEF7h

↑ (8 bytes) Output endpoint_0 buffer

FEF0h

FEEFh TOPBUFF Top of buffer space

↑

Buffer space

↑

F800h STABUFF Start of buffer space

4.3 Endpoint Descriptor Block (EDB−1 to EDB−3)

Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor

block (EDB). Three input and three output EDBs are provided. With the exception of EDB-0 (I/O endpoint-0),

all EDBs are located in SRAM as per Table 4−3. Each EDB contains information describing the X- and

Y-buffers. In addition, each EDB provides general status information.

Table 4−5 describes the EDB entries for EDB−1 to EDB−3. EDB−0 registers are described in Table 4−6.