Datasheet

MCU Memory Map

SLLS519H—January 2010 TUSB3410, TUSB3410I

4 MCU Memory Map

Figure 4−1 illustrates the MCU memory map under boot and normal operation.

NOTE:

The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard

8052 location (0000h to 00FFh). The shaded areas represent the internal ROM/RAM.

• When bit 0 (SDW) of the ROMS register is 0 (boot mode)

The 10K ROM is mapped to address (0x0000−0x27FF) and is duplicated in location (0x8000−0xA7FF) in

code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in data space. Buffers,

MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space.

• When bit 0 (SDW) is 1 (normal mode)

The 10K ROM is mapped to (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to

address range (0x0000−0x3FFF) in code space. Buffers, MMR, and I/O are mapped to address range

(0xF800−0xFFFF) in data space.

Normal Mode (SDW = 1)

0000h

CODE XDATA

16K

Code RAM

Read Only

2K Data

MMR

10K Boot ROM

Boot Mode (SDW = 0)

CODE XDATA

10K Boot ROM

2K Data

MMR

10K Boot ROM

(16K)

Read/Write

27FFh

3FFFh

8000h

A7FFh

F800h

FF7Fh

FF80h

FFFFh

Figure 4−1. MCU Memory Map