Datasheet

I
2
C Port
60
SLLS519H—January 2010TUSB3410, TUSB3410I
N-Byte Read (31 Bytes)
• The data from the device is latched into the I2CDAI register (stop condition is not transmitted).
• Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.
• The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
• This operation repeats 31 times.
Last-Byte Read (Byte 32)
• MCU sets bit 1 (SRD) in the I2STA register to 1. This forces the I
2
C controller to generate a stop
condition after the I2CDAI register contents are received.
• The data from the device is latched into the I2CDAI register (stop condition is transmitted).
• Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.
• The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
10.5 Byte-Write Operation
The byte-write operation involves three phases: device address + EPROM [high byte] phase, EPROM [low
byte] phase, and EPROM [DATA] phase. The following describes the sequence of events to accomplish the
byte-write transaction.
Device Address + EPROM [High Byte]
• The MCU sets clears the SWR bit in the I2CSTA register. This forces the I
2
C controller to not generate
a stop condition after the contents of the I2CDAO register are transmitted.
• The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation).
• The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the
transfer on the SDA line).
• Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
• The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).
• The contents of the I2CDAO register are transmitted to the device (EEPROM high address).
• Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
EPROM [Low Byte]
• The MCU writes the low byte of the EEPROM address into the I2CDAO register.
• Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy).
• The contents of the I2CDAO register are transmitted to the device (EEPROM address).
• Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
EPROM [DATA]
• The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I
2
C controller to generate a stop
condition after the contents of the I2CDAO register are transmitted.
• The data to be written to the EPROM is written by the MCU into the I2CDAO register.
• Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
• The contents of the I2CDAO register are transmitted to the device (EEPROM data).
• Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
• The I
2
C controller generates a stop condition after the contents of the I2CDAO register are
transmitted.