Datasheet

I
2
C Port
57
SLLS519H—January 2010 TUSB3410, TUSB3410I
10 I
2
C Port
10.1 I
2
C Registers
10.1.1 I2CSTA: I
2
C Status and Control Register (Addr:FFF0h)
This register controls the stop condition for read and write operations. In addition, it provides transmitter and
receiver handshake signals with their respective interrupt enable bits.
765 4 32 1 0
RXF RIE ERR 1/4 TXE TIE SRD SWR
R/O R/W R/C R/W R/O R/W R/W R/W
BIT
NAME RESET FUNCTION
0 SWR 0
Stop write condition. This bit determines if the I
2
C controller generates a stop condition when data from the
I2CDAO register is transmitted to an external device.
SWR = 0 Stop condition is not generated when data from the I2CDAO register is shifted out to an external
device.
SWR = 1 Stop condition is generated when data from the I2CDAO register is shifted out to an external device.
1 SRD 0
Stop read condition. This bit determines if the I
2
C controller generates a stop condition when data is received and
loaded into the I2CDAI register.
SRD = 0 Stop condition is not generated when data from the SDA line is shifted into the I2CDAI register.
SRD = 1 Stop condition is generated when data from the SDA line are shifted into the I2CDAI register.
2 TIE 0
I
2
C transmitter empty interrupt enable
TIE = 0
TIE = 1
Interrupt disable
Interrupt enable
3 TXE 1
I
2
C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for polling or it
can generate an interrupt.
TXE = 0 Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDAO register.
TXE = 1 Transmitter is empty. The I
2
C controller sets this bit when the contents of the I2CDAO register are
copied to the SDA shift register.
4 1/4 0
Bus speed selection (see Note 13)
1/4 = 0
1/4 = 1
100-kHz bus speed
400-kHz bus speed
5 ERR 0
Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the MCU.
ERR = 0 No bus error
ERR = 1 Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has no effect.
6 RIE 0
I
2
C receiver ready interrupt enable
RIE = 0
RIE = 1
Interrupt disable
Interrupt enable
7 RXF 0
I
2
C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can generate
an interrupt.
RXF = 0 Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register.
RXF = 1 Receiver contains new data. This bit is set by the I
2
C controller when the received serial data has
been loaded into the I2CDAI register.
NOTE 13: The bootcode automatically sets the I
2
C bus speed to 400 kHz. Only 400-kHz I
2
C EEPROMs can be used.