Datasheet
Interrupts
53
SLLS519H—January 2010 TUSB3410, TUSB3410I
9 Interrupts
9.1 8052 Interrupt and Status Registers
All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that
controls the five interrupt sources. This is also known as IE0 located at S:A8h in the special function register
area. All the additional interrupt sources are ORed together to generate EX0.
Table 9−1. 8052 Interrupt Location Map
INTERRUPT SOURCE DESCRIPTION START ADDRESS COMMENTS
ES UART interrupt 0023h
ET1 Timer-1 interrupt 001Bh
EX1 External interrupt-1 0013h
ET0 Timer-0 interrupt 000Bh
EX0 External interrupt-0 0003h Used for all internal peripherals
Reset 0000h
9.1.1 8052 Standard Interrupt Enable (SIE) Register
765 4 32 1 0
EA RSV RSV ES ET1 EX1 ET0 EX0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 EX0 0
Enable or disable external interrupt-0
EX0 = 0
EX0 = 1
External interrupt-0 is disabled
External interrupt-0 is enabled
1 ET0 0
Enable or disable timer-0 interrupt
ET0 = 0
ET0 = 1
Timer-0 interrupt is disabled
Timer-0 interrupt is enabled
2 EX1 0
Enable or disable external interrupt-1
EX1 = 0
EX1 = 1
External interrupt-1 is disabled
External interrupt-1 is enabled
3 ET1 0
Enable or disable timer-1 interrupt
ET1 = 0
EX1 = 1
Timer-1 interrupt is disabled
Timer-1 interrupt is enabled
4 ES 0
Enable or disable serial port interrupts
ES = 0
ES = 1
Serial-port interrupt is disabled
Serial-port interrupt is enabled
5, 6 RSV 0 Reserved
7 EA 0
Enable or disable all interrupts (global disable)
EA = 0
EA = 1
Disable all interrupts
Each interrupt source is individually controlled
9.1.2 Additional Interrupt Sources
All nonstandard 8052 interrupts (DMA, I
2
C, etc.) are ORed to generate an internal INT0. Furthermore, the
INT0 must be programmed as an active low-level interrupt (not edge-triggered). After reset, if INT0 is not
changed, then it is an edge-triggered interrupt. A vector interrupt register is provided to identify all interrupt
sources (see Section 9.1.3, VECINT: Vector Interrupt Register). Up to 64 interrupt vectors are provided. It is
the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.