Datasheet

UART
49
SLLS519H—January 2010 TUSB3410, TUSB3410I
64-Byte
Y-Buffer
64-Byte
X-Buffer
DMA
DMACDR3
USB
Buffer
Manager
X/Y
48
Receiver
Halt on Error or Time-Out
RDR: 32-Byte FIFO
RTS/DTR = 1
or Xoff Transmitted
RTS/DTR = 0
or Xon Transmitted
Xoff/Xon
CTS/DTR = 1/0
64-Byte
Y-Buffer
64-Byte
X-Buffer
DMA
DMACDR1
SIN
SOUT
TDR
Pause/Run
Host
Figure 7−2. Receiver/Transmitter Data Flow
7.2.2 Hardware Flow Control
Figure 7−3 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS signals
are provided for this purpose. Auto CTS
and auto RTS (and Xon/Xoff) can be enabled/disabled independently
by programming the UART flow control register (FCRL).
TUSB3410
SIN
RTS
SOUT
CTS
External Device
SOUT
CTS
SIN
RTS
Figure 7−3. Auto Flow Control Interconnect
7.2.3 Auto RTS (Receiver Control)
In this mode, the RTS output terminal signals the receiver-FIFO status to an external device. The RTS output
signal is controlled by the high- and low-level marks of the FIFO. When the high-level mark is reached, RTS
goes high, signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is
reached, RTS
goes low, signaling to an external sending device to resume its transfer.
Data transfer from the FIFO to the X-/Y-buffer is performed by the DMA controller. See Section 6.2.1, IN
Transaction (TUSB3410 to Host), for DMA transfer-termination condition.
7.2.4 Auto CTS (Transmitter Control)
In this mode, the CTS input terminal controls the transfer from internal buffer (X or Y) to the TDR. When the
DMA controller transfers data from the Y-buffer to the TDR and the CTS
input terminal goes high, the DMA
controller is suspended until CTS
goes low. Meanwhile, the UBM is transferring data from the host to the
X-buffer. When CTS
goes low, the DMA resumes the transfer. Data transfer continues alternating between
the X- and Y-buffers, without MCU intervention. See Section 6.2.2, OUT Transaction (Host to TUSB3410), for
DMA transfer-termination condition.