Datasheet

UART
47
SLLS519H—January 2010 TUSB3410, TUSB3410I
7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h)
This register contains the high byte of the baud-rate divisor.
765 4 32 1 0
D15
D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 D[15:8] 00h High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.
7.1.11 Baud-Rate Calculation
The following formulas calculate the baud-rate clock and the divisors. The baud-rate clock is derived from the
96-MHz master clock (dividing by 6.5). The table below presents the divisors used to achieve the desired baud
rates, together with the associate rounding errors.
Baud CLK +
96 MHz
6.5
+ 14.76923077 MHz
Divisor +
14.76923077 10
6
DesiredBaudRate 16
Table 7−4. DLL/DLH Values and Resulted Baud Rates
DESIRED BAUD
DLL/DLH VALUE
ACTUAL BAUD
ERROR %
DESIRED
BAUD
RATE
DECIMAL HEXADECIMAL
ACTUAL
BAUD
RATE
ERROR %
1 200 769 0301 1 200.36 0.03
2 400 385 0181 2 397.60 0.01
4 800 192 00C0 4 807.69 0.16
7 200 128 0080 7 211.54 0.16
9 600 96 0060 9 615.38 0.16
14 400 64 0040 14 423.08 0.16
19 200 48 0030 19 230.77 0.16
38 400 24 0018 38 461.54 0.16
57 600 16 0010 57 692.31 0.16
115 200 8 0008 115 384.62 0.16
230 400 4 0004 230 769.23 0.16
460 800 2 0002 461 538.46 0.16
921 600 1 0001 923 076.92 0.16
NOTE: The TUSB3410 does support baud rates lower than 1200 bps, which are not
listed due to less interest.
7.1.12 XON: Xon Register (Addr:FFA9h)
This register contains a value that is compared to the received data stream. Detection of a match interrupts
the MCU (only if the interrupt enable bit is set). This value is also used for Xon transmission.
765 4 32 1 0
D7
D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 D[7:0] 0000 Xon value to be compared to the incoming data stream