Datasheet

UART
41
SLLS519H—January 2010 TUSB3410, TUSB3410I
7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h)
This register provides the flow-control modes of operation (see Table 7−3 for more details).
765 4 32 1 0
485E
DTR RTS RXOF DSR CTS TXOA TXOF
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0 TXOF 0
This bit controls the transmitter Xon/Xoff flow control.
TXOF = 0
TXOF = 1
Disable transmitter Xon/Xoff flow control
Enable transmitter Xon/Xoff flow control
1 TXOA 0
This bit controls the transmitter Xon-on-any/Xoff flow control
TXOA = 0
TXOA = 1
Disable the transmitter Xon-on-any/Xoff flow control
Enable the transmitter Xon-on-any/Xoff flow control
2 CTS 0
Transmitter CTS flow-control enable bit
CTS = 0
CTS = 1
Disables transmitter CTS flow control
CTS
flow control is enabled, that is, when CTS input terminal is high, transmission is halted; when
the CTS
terminal is low, transmission resumes. When loopback mode is enabled, this bit must be
set if flow control is also required.
3 DSR 0
Transmitter DSR flow-control enable bit
DSR = 0
DSR = 1
Disables transmitter DSR flow control
DSR
flow control is enabled, that is, when DSR input terminal is high, transmission is halted; when
the DSR
terminal is low, transmission resumes. When loopback mode is enabled, this bit must be
set if flow control is also required.
4 RXOF 0
This bit controls the receiver Xon/Xoff flow control.
RXOF = 0
RXOF = 1
Receiver does not attempt to match Xon/Xoff characters
Receiver searches for Xon/Xoff characters
5 RTS 0
Receiver RTS flow control enable bit
RTS = 0
RTS = 1
Disables receiver RTS flow control
Receiver RTS
flow control is enabled. RTS output terminal goes high when the receiver FIFO HALT
trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is
reached.
6 DTR 0
Receiver DTR flow-control enable bit
DTR = 0
DTR = 1
Disables receiver DTR flow control
Receiver DTR
flow control is enabled. DTR output terminal goes high when the receiver FIFO HALT
trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is
reached.
7 485E 0
RS-485 enable bit. This bit configures the UART to control external RS-485 transceivers. When configured in
half-duplex mode (485E = 1), RTS
or DTR can be used to enable the RS-485 driver or receiver. See
Figure 3−3.
485E = 0
485E = 1
UART is in normal operation mode (full duplex)
The UART is in half duplex RS-485 mode. In this mode, RTS
and DTR are active with opposite
polarity (when RTS
= 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and
DTR
= 0) 2-bit times before the transmission starts. When the DMA terminates the transmission,
it drives RTS
= 0 (and DTR = 1) after the transmission stops. When 485E is set to 1, bit 4 (DTR)
and bit 5 (RTS) in the MCR register (see Section 7.1.6) have no effect. Also, see bit 1 (RCVE) in
the MCR register.