Datasheet

DMA Controller
36
SLLS519H—January 2010TUSB3410, TUSB3410I
6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel)
(Addr:FFE5h)
This register defines the transaction time-out value. In addition, it contains a completion code that reports any
errors or a time-out condition.
765 4 32 1 0
TEN C4 C3 C2 C1 C0 TXFT OVRUN
R/W R/W R/W R/W R/W R/W R/C R/C
BIT
NAME RESET FUNCTION
0 OVRUN 0
Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6−2)
OVRUN = 0 No overrun condition
OVRUN = 1 Overrun condition detected. When IEN = 0, this bit does not clear bit 7 (EN) in the DMACDR
register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the
MCU writes a 1. Writing a 0 has no effect.
1 TXFT 0
Transfer time-out condition bit (see Table 6−2)
TXFT = 0 DMA stopped transfer without time-out
TXFT =1 DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear bit 7 (EN) in the
DMACDR3 register (see Section 6.1.3); therefore, the DMAC stays enabled, ready for the next
transaction. Clears when the MCU writes a 1. Writing a 0 has no effect.
6−2 C[4:0] 00000b This field defines the transaction time-out value in 1-ms increments. This value is loaded to a down counter every
time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the counter decrements
to zero, then it sets bit 1 (TXFT) = 1 and halts the DMA transfer. The counter starts counting only when bit 7
(TEN) = 1 and bit 7 (EN) = 1 in the DMACDR3 register and the first byte has been received.
00000 = 0-ms time-out
:
:
11111 = 31-ms time-out
7 TEN 0
Transaction time-out counter enable/disable bit
TEN = 0
TEN = 1
Counter is disabled (does not time-out)
Counter is enabled
Table 6−2. DMA IN-Termination Condition
IN TERMINATION TXFT OVRUN COMMENTS
UART error 0 0 UART error condition detected
UART partial packet 1 0 This condition occurs when UART receiver has no more data for the host (data
starvation).
UART overrun 1 1 This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host
is busy).
6.2 Bulk Data I/O Using the EDB
The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters
for IN and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that:
• The MCU initialized the EDBs
• DMA-continuous mode is being used
• Double buffering is being used
• The X/Y toggle is controlled by the UBM