Datasheet

DMA Controller

SLLS519H—January 2010 TUSB3410, TUSB3410I

6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel)

(Addr:FFE4h)

These registers define the EDB number that the DMA uses for data transfer from the UARTS. In addition, these

registers define the data transfer direction and selects X or Y as the transaction buffer.

765 4 32 1 0

EN INE CNT XY T/R E2 E1 E0

R/W R/W R/W R/W R/O R/W R/W R/W

BIT

NAME RESET FUNCTION

2−0 E[2:0] 0 Endpoint descriptor pointer. This field points to a set of EDB registers that are used for a given transfer.

3 T/R 1 This bit is always read as 1. This bit must be written as 0 to update the X/Y buffer bit (bit 4 in this

4 XY 0

X/Y buffer select bit.

XY = 0

XY = 1

Next buffer to transmit/receive is X

Next buffer to transmit/receive is Y

5 CNT 0

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always

be written as 1.

In this mode, the DMA and UBM alternate between the X- and Y-buffers. The UBM sets bit 4 (XY) and the

DMA uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues receiving (to

X-/Y-buffer) without MCU intervention. The DMA terminates the transfer and interrupts the MCU, under the

following conditions:

1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the partial

packet to the host.

2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM transfers the

partial packet to the host.

6 INE 0

DMA interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.

INE = 0 Interrupt is disabled. In addition, bit 0 (OVRUN) and bit 1 (TXFT) in the DMACSR3 register (see

Section 6.1.4) do not clear bit 7 (EN) and the DMAC is not disabled.

INE = 1 Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0 transition

of bit 7 (EN). (When transfer is completed, EN = 0).

7 EN 0

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes, or

when terminated due to error, this bit is cleared. The 1-to-0 transition of this bit generates an interrupt (if

the interrupt is enabled).

EN = 0 DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART

receiver-error condition. When halted, the DMA updates the byte count and sets NAK = 0 in the

input endpoint byte count register. If the termination is due to transaction time-out, then the DMA

generates an interrupt. However, if the termination is due to a UART error condition, then the

DMA does not generate an interrupt. (The UART generates the interrupt.)

EN = 1 Setting this bit starts the DMA transfer.