Datasheet

DMA Controller
34
SLLS519H—January 2010TUSB3410, TUSB3410I
6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel)
(Addr:FFE0h)
These registers define the EDB number that the DMA uses for data transfer to the UARTS. In addition, these
registers define the data transfer direction and selects X or Y as the transaction buffer.
765 4 32 1 0
EN
INE CNT XY T/R E2 E1 E0
R/W R/W R/W R/W R/O R/W R/W R/W
BIT
NAME RESET FUNCTION
2−0 E[2:0] 0 Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.
3 T/R 0 This bit is always 1, indicating that the DMA data transfer is from SRAM to the UART TDR register (see Section 7.1.2).
(The MCU cannot change this bit.)
4 XY 0
X/Y buffer select bit.
XY = 0
XY = 1
Next buffer to transmit/receive is the X buffer
Next buffer to transmit/receive is the Y buffer
5 CNT 0
DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always be
written as 1.
In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA sets bit 4 (XY) and the UBM uses
it for the transfer. The DMA alternates between the X-/Y-buffers and continues transmitting (from X-/Y-buffer) without
MCU intervention. The DMA terminates, and interrupts the MCU, under the following conditions:
1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and interrupt the MCU on
completion.
2. Transaction timer expires. The DMA interrupts the MCU.
6 INE 0 DMA Interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.
INE = 0 Interrupt is disabled. In addition, bit 0 (PPKT) in the DMACSR1 register (see Section 6.1.2) does not clear
bit 7 (EN) and the DMAC is not disabled.
INE = 1 Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the
bit 7 (EN). (When transfer is completed, EN = 0.)
7 EN 0
DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or when it
is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if the interrupt is
enabled).
EN = 0 DMA is halted. The DMA is halted when the byte count reaches zero or transaction time-out occurs. When
halted, the DMA updates the byte count, sets NAK = 0 in the output endpoint byte count register, and
interrupts the MCU (if bit 6 (INE) = 1).
EN = 1 Setting this bit starts the DMA transfer.
6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel)
(Addr:FFE1h)
This register defines the transaction time-out value. In addition, it contains a completion code that reports any
errors or a time-out condition.
765 4 32 1 0
0
0 0 0 0 0 0 PPKT
RRR R RR R R/C
BIT
NAME RESET FUNCTION
0 PPKT 0
Partial packet condition bit. This bit is set by the DMA and cleared by the MCU.
PPKT = 0 No partial-packet condition
PPKT = 1 Partial-packet condition detected. When INE = 0, this bit does not clear bit 7 (EN) in the DMACDR1
register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU
writes a 1. Writing a 0 has no effect.
7−1 − 0 These bits are read-only and return 0s when read.