Datasheet

USB Registers
31
SLLS519H—January 2010 TUSB3410, TUSB3410I
5.15 Function Reset And Power-Up Reset Interconnect
Figure 5−1 represents the logical connection of the USB-function reset (USBR) signal and the power-up reset
(RESET
) terminal. The internal RESET signal is generated from the RESET terminal (PURS signal) or from
the USB reset (USBR
signal). The USBR can be enabled or disabled by bit 4 (FRSTE) in the USBCTL register
(see Section 5.4) (on power up, FRSTE = 0). The internal RESET
is used to reset all registers and logic, with
the exception of the USBCTL and MODECNFG registers which are cleared by the PURS
signal only.
USBCTL Register
MODECNFG Register
PURS
USBR
RESET
MCU
FRSTE
USB Function Reset
To Internal MMRs
RESET
G2
WDD[5:0]
WDT Reset
Figure 5−1. Reset Diagram
5.16 Pullup Resistor Connect/Disconnect
The TUSB3410 enumeration can be activated by the MCU (there is no need to disconnect the cable
physically). Figure 5−2 represents the implementation of the TUSB3410 connect and disconnect from a USB
up-stream port. When bit 7 (CONT) is 1 in the USBCTL register (see Section 5.4), the CMOS driver sources
V
DD to the pullup resistor (PUR terminal) presenting a normal connect condition to the USB host. When CONT
is 0, the PUR terminal is driven low. In this state, the 1.5-kΩ resistor is connected to GND, resulting in the device
disconnection state. The PUR driver is a CMOS driver that can provide (V
DD − 0.1 V) minimum at 8-mA source
current.
HOST
D+
D−
15 kΩ
TUSB3410
1.5 kΩ
CMOS
PUR
CONT Bit
DP0
DM0
Figure 5−2. Pullup Resistor Connect/Disconnect Circuit