Datasheet

MCU Memory Map
15
SLLS519H—January 2010 TUSB3410, TUSB3410I
and writes to the 16K RAM in XDATA space. If it does not contain the code, then the MCU proceeds to boot
from the USB.
Once the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register. This switches the memory map
to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from location
0000h. Once the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register. This connects the
device to the USB and results in normal USB device enumeration.
4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)
A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms,
then the WDT counter resets the MCU (see Figure 5−1). The watchdog timer is enabled by default and can
be disabled by writing a pattern of 101010b into the WDD[5:0] bits. The 1-ms clock for the watchdog timer is
generated from the SOF pulses. Therefore, in order for the watchdog timer to count, bit 7 (CONT) in the
USBCTL register (see Section 5.4) must be set.
765 4 32 1 0
WDD0 WDR WDD5 WDD4 WDD3 WDD2 WDD1 WDT
R/W R/C R/W R/W R/W R/W R/W W/O
BIT
NAME RESET FUNCTION
0 WDT 0 MCU must write a 1 to this bit to prevent the watchdog timer from resetting the MCU. If the MCU does not
write a 1 in a period of 128 ms, the watchdog timer resets the device. Writing a 0 has no effect on the
watchdog timer. (The watchdog timer is a 7-bit counter using a 1-ms CLK.) This bit is read as 0.
5−1 WDD[5:1] 00000 These bits disable the watchdog timer. For the timer to be disabled these bits must be set to 10101b and
bit 7 (WDD0) must also be set to 0. If any other pattern is present, then the watchdog timer is in operation.
6 WDR 0
Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog
timer reset.
WDR = 0 A power-up reset occurred
WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no
effect.
7 WDD0 1 This bit is one of the six disable bits for the watchdog timer. This bit must be cleared in order for the
watchdog timer to be disabled.
4.2 Buffers + I/O RAM Map
The address range from F800h to FFFFh (2K bytes) is reserved for data buffers, setup packet, endpoint
descriptors block (EDB), and all I/O. There are 128 locations reserved for memory-mapped registers (MMR).
Table 4−2 represents the XDATA space allocation and access restriction for the DMA, USB buffer manager
(UBM), and MCU.
Table 4−2. XDATA Space
DESCRIPTION ADDRESS RANGE UBM ACCESS DMA ACCESS MCU ACCESS
Internal MMRs
(Memory-Mapped Registers)
FFFFh−FF80h
No
(Only EDB-0)
No
(only data register and EDB-0)
Yes
EDB
(Endpoint Descriptors Block)
FF7Fh−FF08h Only for EDB update Only for EDB update Yes
Setup Packet FF07h−FF00h Yes No Yes
Input Endpoint-0 Buffer FEFFh−FEF8h Yes Yes Yes
Output Endpoint-0 Buffer FEF7h−FEF0h Yes Yes Yes
Data Buffers FEEFh−F800h Yes Yes Yes