Datasheet

www.ti.com
3.3 V
1.5 kΩ
D+
D-
DP0
DM0
1.5 kΩ
D+
D-
DP0
DM0
Bus PWR
(5 V)
PUR
(a) (b)
4.2 Reset Timing
TUSB3210
Universal Serial Bus
General-Purpose Device Controller
SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007
Figure 4-3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode
There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μ s.
At power up, this time is measured from the time the power ramps up to 90% of the nominal V
CC
until the
reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 μ s of
the reset window. The third requirement is that, according to the USB specification, the device must be
ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must
come out of reset, load any pertinent data from the I
2
C EEPROM device, and transfer execution to the
application firmware if any is present. Because the latter two events can require significant time, the
amount of which can change from system to system, TI recommends having the device come out of reset
within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal should rise to
1.8 V within 30 ms.
These requirements are depicted in Figure 4-4 . Notice that when using a 12-MHz crystal or the 48-MHz
oscillator, the clock signal may take several milliseconds to ramp up and become valid after power up.
Therefore, the reset window may need to be elongated up to 10 ms or more to ensure that there is a
60- μ s overlap with a valid clock.
Submit Documentation Feedback Application 41