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2.5 Endpoint-0 Descriptor Registers
2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register
TUSB3210
Universal Serial Bus
General-Purpose Device Controller
SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007
Unlike EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described by a set
of four registers (two for output and two for input). Table 2-5 defines the registers and their respective
addresses used for EDB-0 description. EDB-0 has no Base-Address Register, because these addresses
are hardwired to FEF8 and FEF0. Note that the bit positions have been preserved to provide consistency
with EDB-n (n = 1 to 3).
Table 2-5. Input/Output EDB-0 Registers
ADDRESS REGISTER NAME DESCRIPTION BASE ADDRESS
FF83 OEPBCNT_0 Output endpoint_0: byte-count register
FF82 OEPCNFG_0 Output endpoint_0: configuration register FEF0
FF81 IEPBCNT_0 Input endpoint_0: byte-count register
FF80 IEPCNFG_0 Input endpoint_0: configuration register FEF8
7 6 5 4 3 2 1 0
UBME RSV TOGLE RSV STALL USBIE RSV RSV
R/W R/O R/O R/O R/W R/W R/O R/O
BIT NAME RESET FUNCTION
1–0 RSV 0 Reserved
2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU
USBIE = 0 No interrupt
USBIE = 1 Interrupt on transaction completion
3 STALL 0 USB stall condition indication. Set/cleared by the MCU
STALL = 0 No stall
STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared
automatically by the next setup transaction.
4 RSV 0 Reserved
5 TOGLE 0 USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.
6 RSV 0 Reserved
7 UBME 0 UBM enable/disable bit. Set/cleared by the MCU
UBME = 0 UBM cannot use this endpoint.
UBME = 1 UBM can use this endpoint.
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