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2.2.6 PCON: Power Control Register (at SFR 87h)
TUSB3210
Universal Serial Bus
General-Purpose Device Controller
SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007
7 6 5 4 3 2 1 0
WDE WDR RSV RSV RSV RSV RSV WDT
R/W R/W R/O R/O R/O R/O R/O W/O
BIT NAME RESET FUNCTION
0 WDT 0 The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If the MCU does not write a 1
in a period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit
counter using a 1-ms CLK.) This bit is read as 0.
5–1 RSV 0 Reserved = 0
6 WDR 0 Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog timer
reset.
WDR = 0 A power-up or USB reset occurred.
WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no
effect.
7 WDE 0 Watchdog timer enable.
WDE = 0 Disabled
WDE = 1 Enabled
7 6 5 4 3 2 1 0
SMOD RSV RSV RSV GF1 GF0 RSV IDL
R/W R/O R/O R/O R/W R/W R/O R/W
BIT NAME RESET FUNCTION
0 IDL 0 MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt.
IDL = 0 The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is
asserted for at least 400 μ s.
IDL = 1 The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the
WDT is suspended. When in suspend mode, only INT1 can be used to exit from idle state
and generate an interrupt. INT1 must be asserted for at least 400 μ s for the interrupt to be
recognized.
1 RSV 0 Reserved
3–2 GF[1:0] 00 General-purpose bits. The MCU can write and read them.
6–4 RSV 0 Reserved
7 SMOD 0 Double baud-rate control bit. For more information, see the UART serial interface in the M8052 core
specification.
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