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2.2 Miscellaneous Registers
2.2.1 TUSB3210 Boot Operation
2.2.2 MCNFG: MCU Configuration Register
TUSB3210
Universal Serial Bus
General-Purpose Device Controller
SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007
Because the code space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must
be loaded from an external source. Two options for booting are available: an external serial EEPROM
source can be connected to the I
2
C bus, or the host can be used via the USB. On device reset, the SDW
bit (in the ROM register) and the CONT bit in the USB control register (USBCTL) are cleared. This
configures the memory space to boot mode (see memory map, Table 2-2 ) and keeps the device
disconnected from the host.
The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to
XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests to
determine if it contains the code (test for boot signature). If it contains the code, the MCU reads from
EEPROM and writes to the 8K RAM in XDATA space. If not, the MCU proceeds to boot from the USB.
Once the code is loaded, the MCU sets SDW to 1. This switches the memory map to normal mode; i.e.,
the 8K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the
switch is done, the MCU sets CONT to 1 (in USBCTL register) This connects the device to the USB bus,
resulting in the normal USB device enumeration.
This register is used to control the MCU clock rate. (R/O notation indicates read only by the MCU.)
7 6 5 4 3 2 1 0
RSV XINT RSV R3 R2 R1 R0 SDW
R/W R/W R/O R/O R/O R/O R/O R/W
BIT NAME RESET FUNCTION
0 SDW 0 This bit enables/disables boot ROM.
SDW = 0 When clear, the MCU executes from the 6K boot ROM space. The boot ROM appears in
two locations: 0000 and 8000h. The 8K RAM is mapped to XDATA space; therefore,
read/write operation is possible. This bit is set by the MCU after the RAM load is completed.
The MCU cannot clear this bit. It is cleared on power-up reset or function reset.
SDW = 1 When set by the MCU, the 6K boot ROM maps to location 8000h, and the 8K RAM is
mapped to code space, starting at location 0000h. At this point, the MCU executes from
RAM, and write operation is disabled (no write operation is possible in code space).
4–1 R[3:0] No effect These bits reflect the device revision number.
5 RSV 0 Reserved
6 XINT 0 INT1 source control bit
XINT = 0 INT1 is connected to the P3.3 pin and operates as a standard INT1 interrupt.
XINT = 1 INT1 is connected to the OR of the port-2 inputs.
7 RSV 0 Reserved
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