Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller (user-defined) TUSB3210 USB microcontroller LQFP 64

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

Data Manual

August 2007 DIBU

SLLS466F

Summary of content (46 pages)

PAGE 1
TUSB3210 Universal Serial Bus General-Purpose Device Controller Data Manual August 2007 DIBU SLLS466F
PAGE 2
TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Contents 1 Introduction......................................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 2 Functional Description ........................................................................................................ 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2 Features ......................................
PAGE 3
TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.11 3 35 35 35 35 36 36 37 37 Specifications .................................................................................................................... 39 3.1 3.2 3.3 4 2.10.3 I2CDAI: I 2C Data-Input Register .............................................................................. 2.10.4 I2CDAO: I 2C Data-Output Register .......................................................
PAGE 4
TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 List of Figures 1-1 1-2 2-1 2-2 2-3 2-4 2-5 4-1 4-2 4-3 4-4 4 ........................................................................................................ 8 Terminal Assignments ............................................................................................................. 9 MCU Memory Map (TUSB3210) ......................................................................
PAGE 5
TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 List of Tables 1-1 Terminal Functions ................................................................................................................. 9 1-2 Test0/Test1 Functions ............................................................................................................ 10 2-1 XDATA Space .......................................................................................
PAGE 6
TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 6 List of Tables Submit Documentation Feedback
PAGE 7
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 1 Introduction 1.1 Features • Multiproduct Support With One Code and One Chip (up to 16 Products With One Chip) • Fully Compliant With USB 2.
PAGE 8
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 1.4 Device Information Functional Block Diagram 12 MHz Clock Oscillator PLL and Dividers USB-0 Reset, Interrupt and WDT 8052 Core USB TxR 6K × 8 ROM 8 8K × 8 RAM 8 8 RSTI 2 × 16-Bit Timers Port 0 8 P0.[7:0] Port 1 8 P1.[7:0] Port 2 8 P2.[7:0] Port 3 8 P3.
PAGE 9
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 GND P1.7 P1.6 VCC VREN 1.8VDD P1.5 P1.4 P1.3 P1.2 PM PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 1 2 3 4 5 17 6 7 8 9 10 11 12 13 14 15 16 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 GND P2.1 P2.
PAGE 10
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Table 1-1. Terminal Functions (continued) TERMINAL NAME P2.[0:7] NO. I/O DESCRIPTION 22, 23, 25, 26, 27, 28, 29, 30 I/O General-purpose I/O port 2 bits 0–7, Schmitt-trigger input, 100-μA active pullup, open-drain output (2) 58 I/O P3.0: General-purpose I/O port 3 bit 0, Schmitt-trigger input, 100-μA active pullup, open-drain output (2) P3.0/S0/RXD S0: See Section 2.6.5.
PAGE 11
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 1.5 Revision History Revision Date Changes February 2001 Initial release A February 2003 1. Removed most references to ROM version, including the MCU Memory Map (ROM Version) figure. 2. Clarified pin names and descriptions for pins 8 (S2), 9 (S3), 21 (GND), 37 (VDD18), 57 (P3.1/S1/TXD), and 58 (P3.0/S0/RXD). 3. Removed NOTE from cover page. 4.
PAGE 12
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2 Functional Description 2.1 MCU Memory Map Figure 2-1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256 bytes of IDATA are not shown because it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM.
PAGE 13
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.2 Miscellaneous Registers 2.2.1 TUSB3210 Boot Operation Because the code space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from an external source. Two options for booting are available: an external serial EEPROM source can be connected to the I2C bus, or the host can be used via the USB.
PAGE 14
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) PUR_0: GPIO pullup register for port 0 PUR_1: GPIO pullup register for port 1 PUR_2: GPIO pullup register for port 2 PUR_3: GPIO pullup register for port 3 7 6 5 4 3 2 1 0 PORT_n.7 PORT_n.6 PORT_n.5 PORT_n.4 PORT_n.3 PORT_n.2 PORT_n.1 PORT_n.
PAGE 15
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 7 6 5 4 3 2 1 0 WDE WDR RSV RSV RSV RSV RSV WDT R/W R/W R/O R/O R/O R/O R/O W/O BIT NAME RESET FUNCTION 0 WDT 0 The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If the MCU does not write a 1 in a period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit counter using a 1-ms CLK.
PAGE 16
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.3 Buffers + I/O RAM Map The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB), and all I/O. RAM space of 512 bytes [FD80–FF7F] is used for EDB and buffers. The FF80–FFFF range is used for memory-mapped registers (MMR). Table 2-1 represents the internal XDATA space allocation. Table 2-1.
PAGE 17
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Table 2-2.
PAGE 18
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four input and four output EDBs are provided. With the exception of EDB-0 (I/O endpoint 0), all EDBs are located in SRAM as shown in Table 2-3. Each EDB contains information describing the X and Y buffers.
PAGE 19
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Table 2-4 lists the EDB entries for EDB-1 to EDB-3. EDB-0 registers are described separately. Table 2-4. EDB Entries in RAM (n = 1 to 3) Offset 2.4.
PAGE 20
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7–0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the MCU.
PAGE 21
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.4.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 6–0 C[6:0] x Y-Buffer Byte count: 000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.
PAGE 22
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 BIT NAME RESET 6 ISO x ISO = 0 7 UBME x UBM enable/disable bit. Set/cleared by the MCU. 2.4.8 UBME = 0 UBM cannot use this endpoint. UBME = 1 UBM can use this endpoint.
PAGE 23
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7–0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by the MCU.
PAGE 24
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.5 Endpoint-0 Descriptor Registers Unlike EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described by a set of four registers (two for output and two for input). Table 2-5 defines the registers and their respective addresses used for EDB-0 description. EDB-0 has no Base-Address Register, because these addresses are hardwired to FEF8 and FEF0.
PAGE 25
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.5.2 IEPBCNT_0: Input Endpoint-0 Byte-Count Register 7 6 5 4 3 2 1 0 NAK RSV RSV RSV C3 C2 C1 C0 R/W R/O R/O R/O R/W R/W R/W R/W BIT NAME RESET 3–0 C[3:0] 0000 6–4 RSV 0 Reserved 7 NAK 1 NAK = 0 Buffer contains a valid packet for host-in transaction. NAK = 1 Buffer is empty (host-in request is NAK). 2.5.
PAGE 26
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.5.4 OEPBCNT_0: Output Endpoint-0 Byte-Count Register 7 6 5 4 3 2 1 0 NAK RSV RSV RSV C3 C2 C1 C0 R/W R/O R/O R/O R/W R/W R/W R/W BIT NAME RESET 3–0 C[3:0] 0000 6–4 RSV 0 Reserved = 0 7 NAK 1 NAK = 0 No valid data in buffer. Ready for host-out NAK = 1 Buffer contains a valid packet from host (NAK the host). 2.
PAGE 27
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.6.2 USBSTA: USB Status Register All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C notation indicates read and clear only by the MCU).
PAGE 28
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.6.
PAGE 29
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 BIT NAME RESET 3 RWE 0 4 FRSTE 5 1 RWUP FUNCTION Remote wake-up enable bit RWE = 0 MCU clears this bit when host sends command to clear the feature. RWE = 1 MCU writes 1 to this bit when host sends set device feature command to enable the remote wake-up feature Function reset connection bit. This bit connects/disconnects the USB function reset from the MCU reset.
PAGE 30
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 USBCTL Register MCNFG Register All Internal MMR RST PURS RESET USBR MCU WDT Reset USB Function Reset WDE FRSTE Figure 2-2. Reset Diagram 2.8 Pullup Resistor Connect/Disconnect After reading firmware into RAM, the TUSB3210 can re-enumerate using the new firmware (no need to physically disconnect and re-connect the cable).
PAGE 31
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Table 2-7. 8052 Interrupt Location Map (continued) INTERRUPT SOURCE DESCRIPTION START ADDRESS ES UART interrupt 0023h 001Bh ET1 Timer-1 interrupt EX1 Internal INT1 or INT1 0013h ET0 Timer-0 interrupt 000Bh INT0 Internal INT0 0003h Reset 2.9.
PAGE 32
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.9.3 VECINT: Vector Interrupt Register This register contains a vector value identifying the internal interrupt source that trapped to location 0003h. Writing any value to this register removes the vector and updates the next vector value (if another interrupt is pending). Note that the vector value is offset. Therefore, its value is in increments of two (bit 0 is set to 0).
PAGE 33
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.9.4 Logical Interrupt Connection Diagram (INT0) Figure 2-4 represents the logical connection of the interrupt sources and the relation of the logical connection with INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hard wired. Vector 46h is the highest and 12h is the lowest.
PAGE 34
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.10 I2C Registers The TUSB3210 only supports a master-slave relationship; therefore, it does not support bus arbitration. 2.10.1 I2CSTA: I 2C Status and Control Register This register is used to control the stop condition for read and write operations. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits.
PAGE 35
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 2.10.2 I2CADR: I 2C Address Register This register holds the device address and the read/write command bit. 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 0 R/W 0 7–1 A[6:0] FUNCTION Read/write command bit R/W = 0 Write operation R/W = 1 Read operation 000 0000 Seven address bits for device addressing 2.10.
PAGE 36
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 SDA). 7. The content of the I2CDAO register is transmitted to the EEPROM (EEPROM address). 8. The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been transmitted. 9. No stop condition is generated. EEPROM [Low Byte] 1. The MCU writes the low byte of the EEPROM address into the I2CDAO register. 2.
PAGE 37
www.ti.com TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 d. The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0). 2.11.4 Write Operation (Serial EEPROM) The byte write operation involves three phases: 1) device address + EEPROM [high byte] phase, 2) EEPROM [low byte] phase, and 3) EEPROM [DATA].
PAGE 38
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 Device Address + EEPROM [High Byte] 1. The MCU sets I2CSTA[SWR] = 0. This prevents the I2C controller from generating a stop condition after the content of the I2CDAO register is transmitted. 2. The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation). 3. The MCU writes the high byte of the EEPROM address into the I2CDAO register. 4.
PAGE 39
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 3 Specifications 3.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage –0.5 4 V VI Input voltage –0.5 VCC + 0.5 V VO Output voltage –0.5 VCC + 0.
PAGE 40
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 4 Application 4.1 Examples Figure 4-1 illustrates the port-3 pins that are assigned to drive the four example LEDs. For the connection example shown, P3[5:2] can sink up to 8 mA each (open-drain outputs). Figure 4-2 illustrates the partial connection bus power mode.
PAGE 41
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 PUR Bus PWR (5 V) 3.3 V 1.5 kΩ 1.5 kΩ D+ DP0 D+ DP0 D- DM0 D- DM0 (a) (b) Figure 4-3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode 4.2 Reset Timing There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs.
PAGE 42
TUSB3210 Universal Serial Bus General-Purpose Device Controller www.ti.com SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 3.3 V VCC CLK 90% RESET 1.8 V 1.2 V 0V t >60 µs 100 µs < RESET TIME RESET TIME < 30 ms Figure 4-4.
PAGE 43
PACKAGE OPTION ADDENDUM www.ti.
PAGE 44
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 45
PAGE 46
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.