Datasheet

2−27
• The RXF bit in I2CSTA is set, and interrupts the MCU, indicating that data is available.
• The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0).
• This operation repeats 31 times.
3. Last-Byte Read (byte 32)
• The MCU sets I2CSTA[SRD] = 1. This forces the I
2
C controller to generate a stop condition after the
I2CDAI register is received.
• Data from the device is latched into the I2CDAI register (stop condition is transmitted).
• The RXF bit in I2CSTA is set, and interrupts the MCU, indicating that data is available.
• The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0).
2.11.4 Write Operation (Serial EEPROM)
The byte write operation involves three phases: 1) device address + EEPROM [high byte] phase, 2) EEPROM [low
byte] phase, and 3) EEPROM [DATA]. The following describes the sequence of events to accomplish the byte write
transaction:
Device Address + EEPROM [high byte]
• The MCU sets I2CSTA[SWR] = 0. This prevents the I
2
C controller from generating a stop condition after
the content of the I2CDAO register is transmitted.
• The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).
• The MCU writes the high byte of the EEPROM address into the I2CDAO register, starting the transfer on
the SDA line.
• The TXE bit in I2CSTA is cleared, indicating busy.
• The content of the I2CADR register is transmitted to the device (preceded by a start condition on SDA).
• The content of the I2CDAO register is transmitted to the device (EEPROM high-address).
• The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been
transmitted.
EEPROM [low byte]
• The MCU writes the low byte of the EEPROM address into the I2CDAO register.
• The TXE bit in I2CSTA is cleared, indicating busy.
• The content of the I2CDAO register is transmitted to the device (EEPROM address).
• The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been
transmitted.