Datasheet

2−25
2.10.2 I2CADR: I
2
C Address Register
This register holds the device address and the read/write command bit.
76 5 43210
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0 R/W 0
Read/write command bit.
0
R/W
0
R/W = 0 Write operation
R/W = 1 Read operation
7−1 A[6:0] 0000000 Seven address bits for device addressing
2.10.3 I2CDAI: I
2
C Data-Input Register
This register holds the received data from an external device.
76 5 43210
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT NAME RESET FUNCTION
7−0 D[7:0] 0 8-bit input data from an I
2
C device
2.10.4 I2CDAO: I
2
C Data-Output Register
This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the
SDA line.
76 5 43210
D7
D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
7−0 D[7:0] 0 8-bit output data to an I
2
C device
2.11 Read/Write Operations
2.11.1 Read Operation (Serial EEPROM)
A serial read requires a dummy byte write sequence to load in the 16-bit data word address. Once the device address
word and data word are clocked out and acknowledged by the device, the MCU starts a current address sequence.
The following describes the sequence of events to accomplish this transaction:
Device Address + EEPROM [high byte]
• The MCU sets I2CSTA[SRD] = 0. This prevents the I
2
C controller from generating a stop condition after the
content of the I2CDAI register is received.
• The MCU sets I2CSTA[SWR] = 0. This prevents the I
2
C controller from generating a stop condition after
the content of the I2CDAO register is transmitted.
• The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).
• The MCU writes the high byte of the EEPROM address into the I2CDAO register, starting the transfer on
the SDA line.