Datasheet

2−19

Table 2−6. External Pins Mapping to S[3:0] in VIDSTA Register

VIDSTA REGISTER PIN

COMMENTS

S[3:0] NO. NAME

COMMENTS

S0 58 P3.0 Dual function, P3.0 I/O or S0 input

S1 57 P3.1 Dual function, P3.1 I/O or S1 input

S2 8 S2 S2-pin is input

S3 9 S3 S3-pin is input

2.7 Function Reset and Power-Up Reset Interconnect

Figure 2−2 represents the logical connection of USB-function reset (USBR) and power-up reset (RST) pins. The

internal RESET

signal is generated from the RST pin (PURS signal) or from the USB reset (USBR signal). The USBR

can be enabled or disabled by the FRSTE bit in the USBCTL register (on power up FRSTE = 0). The internal RESET

is used to reset all registers and logic, with the exception of the USBCTL and MISCTL registers. The USBCTL and

MCU configuration registers (MCNFG) are cleared by the PURS

signal only.

WDT Reset

WDE

PURS

USBCTL Register

MCNFG Register

USB Function Reset

FRSTE

RESET

MCU

All Internal MMR

RST

USBR

Figure 2−2. Reset Diagram

2.8 Pullup Resistor Connect/Disconnect

After reading firmware into RAM, the TUSB2136 can reenumerate using the new firmware (no need to physically

disconnect and re-connect the cable). Figure 2−3 shows an equivalent circuit implementation for Connect and

Disconnect from a USB upstream port (also see Figure 4−4b). When the CONT bit in the USBCTL register is 1, the

CMOS driver sources V

DD to the pullup resistor (PUR pin), presenting a normal connect condition to the USB hub

(high speed). When the CONT bit is 0, the PUR pin is driven low. In this state, the 1.5-kΩ resistor is connected to GND,

resulting in device disconnection state. The PUR driver is a CMOS driver that can provide V

DD − 0.1 V minimum at

8-mA source current.