Datasheet

2−7
Table 2−4 illustrates the EDB entries for EDB-1 to EDB-3. EDB-0 registers are described separately.
Table 2−4. EDB Entries in RAM (n = 1 to 3)
Offset ENTRY NAME DESCRIPTION
07 EPSIZXY_n I/O endpoint_n: X/Y buffer size
06 EPBCTY_n I/O endpoint_n: Y byte count
05 EPBBAY_n I/O endpoint_n: Y buffer base address
04 SPARE Not used
03 SPARE Not used
02 EPBCTX_n I/O endpoint_n: X byte count
01 EPBBAX_n I/O endpoint_n: X buffer base address
00 EPCNF_n I/O endpoint_n: configuration
2.4.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)
76 5 43210
UBME ISO TOGLE DBUF STALL USBIE RSV RSV
R/W R/W R/W R/W R/W R/W R/O R/O
BIT NAME RESET FUNCTION
1−0 RSV x Reserved = 0
2 USBIE x
USB interrupt enable on transaction completion. Set/clear by MCU.
2
USBIE
x
USBIE = 0 No interrupt
USBIE = 1 Interrupt on transaction completion
3 STALL 0
USB stall condition indication. Set/clear by MCU.
3
STALL
0
STALL = 0 No stall
STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared by
the MCU.
4 DBUF x
Double buffer enable. Set/clear by MCU.
4
DBUF
x
DBUF = 0 Primary buffer only (X-buffer only)
DBUF = 1 Toggle bit selects buffer
5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1
6 ISO x ISO = 0 Non-isochronous transfer. This bit must be cleared by the MCU because only
non-isochronous transfer is supported.
7 UBME x
USB buffer manager (UBM) enable/disable bit. Set/clear by MCU.
7
UBME
x
UBME = 0 UBM cannot use this endpoint.
UBME = 1 UBM can use this endpoint.
2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address (n = 1 to 3)
76 5 43210
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
7−0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11-bits). This value is set by the
MCU. UBM or DMA uses this value as the start address of a given transaction. Furthermore, UBM or DMA
does not change this value at the end of a transaction.