Datasheet

2−4
2.2.6 PCON: Power Control Register (at SFR 87h)
76 5 43210
SMOD RSV RSV RSV GF1 GF0 RSV IDL
R/W R/O R/O R/O R/W R/W R/O R/W
BIT NAME RESET FUNCTION
0 IDL 0
MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt.
0
IDL
0
IDL = 0 The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is
asserted for at least 400 µs.
IDL = 1 The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the
WDT is suspended. When in suspend mode, only INT1
can be used to exit from the idle state
and generate an interrupt. INT1
must be asserted for at least 400 µs for the interrupt to be
recognized.
1 RSV 0 Reserved
3−2 GF[1:0] 00 General-purpose bits. The MCU can write and read them.
6−4 RSV 0 Reserved
7 SMOD 0 Double baud-rate control bit. For more information see the UART serial interface in the M8052 core
specification.
2.3 Buffers + I/O RAM Map
The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB),
and all I/O. RAM space of 512 bytes [FD80−FF7F] is used for EDB and buffers. The FF80−FFFF range is used for
memory-mapped registers (MMR). Table 2−1 represents the internal XDATA space allocation.
Table 2−1. XDATA Space
DESCRIPTION ADDRESS RANGE
FFFF
Internal
Internal
memory mapped registers
↑
memory mapped registers
(MMR)
↑
memory mapped registers
(MMR)
FF80
FF7F
Endpoint descriptor blocks
Endpoint descriptor blocks
(EDB)
↑
(EDB)
FF08
FF07
Setup packet buffer
↑
Setup packet buffer
FF00
FEFF
512 -Byte
Input endpoint-0 buffer
↑
512 -Byte
RAM
Input endpoint-0 buffer
FEF8
RAM
FEF7
Output endpoint-0 buffer
↑
Output endpoint-0 buffer
FEF0
FEEF
Data buffers
Data buffers
(368 bytes)
↑
Data buffers
(368 bytes)
↑
(368 bytes)
FD80