Datasheet

2−3
2.2.4 INTCFG: Interrupt Configuration
76 5 43210
RSV RSV RSV RSV I3 I2 I1 I0
R/O R/O R/O R/O R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0−3 I[3:0] 0010 The MCU can write to this register to set the interrupt delay time for port 2 on the MCU. The value of the
lower nibble represents the delay in ms. Default after reset is 2 ms.
4−7 RSV 0 Reserved
2.2.5 WDCSR: Watchdog Timer, Control, and Status Register
A watchdog timer (WDT) with 1-ms clock is provided. The watchdog timer only works when a USB start-of-frame has
been detected by the TUSB3210. If this register is not accessed for a period of 32 ms, the WDT counter resets the
MCU (see Figure 2−2, Reset Diagram). When the IDL bit in PCON is set, the WDT is suspended until an interrupt
is detected. At this point, the IDL bit is cleared and the WDT resumes operation. The WDE bit of this register is cleared
only on power-up or USB reset (if enabled). When the MCU writes a 1 to the WDE bit of this register the WDT starts
running.
76 5 43210
WDE WDR RSV RSV RSV RSV RSV WDT
R/W R/W R/O R/O R/O R/O R/O W/O
BIT NAME RESET FUNCTION
0 WDT 0 The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1 in a
period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (The WDT is a 5-bit
counter using a 1-ms CLK). This bit is read as 0.
5−1 RSV 0 Reserved
6 WDR 0
Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog
timer reset.
WDR = 0 A power-up or USB reset occurred.
WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has
no effect.
7 WDE 0
Watchdog timer enable
7
WDE
0
WDE = 0 Disabled
WDE = 1 Enabled