Datasheet

TUSB1310A
www.ti.com SLLSE32E –NOVEMBER 2010–REVISED JULY 2012
2 PIN DESCRIPTIONS
TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PD, PU Internal pull-down / pull-up
S Strapping pin
P Power Supply
G Ground
2.1 Configuration Pins
The configuration pins are not latched by RESETN.
Table 2-1. Configuration Pins
SIGNAL NAME TYPE PIN NO. MODE NAME DESCRIPTION
PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver.
PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver.
2.2 PIPE
The TUSB1310A supports 16-bit SDR mode with a 250-MHz clock.
Table 2-2. PIPE Signal Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is
TX_CLK I K1
the same as PCLK frequency. The rising edge of the clock is the reference for all signals.
TX_DATA15 G2
TX_DATA14 H2
TX_DATA13 H1
TX_DATA12 J2
TX_DATA11 L3
TX_DATA10 L2
TX_DATA9 M2
Parallel USB SuperSpeed data input bus.
TX_DATA8 M1
I The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to
TX_DATA7 N1
be transmitted, and TX_DATA15-8 is the second symbol.
TX_DATA6 P1
TX_DATA5 N2
TX_DATA4 P2
TX_DATA3 N3
TX_DATA2 P3
TX_DATA1 N4
TX_DATA0 P5
TX_DATAK1 G1
Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of
I
TX_DATA, TX_DATAK1 to the upper byte.
TX_DATAK0 J1
Parallel interface data clock. All data movement across the parallel PIPE is synchronous
PCLK O A6 to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference
for all signals.
Copyright © 2010–2012, Texas Instruments Incorporated PIN DESCRIPTIONS 9
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Product Folder Link(s): TUSB1310A