Datasheet

PCLK
RX_DATA15-0
RX_DATAK1-0
RX_VALID
RX_STATUS2-0
PHY_STATUS
Valid Data
Tcyc3
Tdly3
TUSB1310A
SLLSE32E –NOVEMBER 2010–REVISED JULY 2012 www.ti.com
6.5.3 PIPE Receive
Figure 6-3. PIPE Receive Timing
Table 6-3. PIPE Receive Timing
SYMBOL DESCRIPTION MIN TYP MAX UNIT
Tcyc3 PCLK Period 4 ns
Tdty3 PCLK Duty Cycle 50 %
PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID,
Tdly3 1 2 ns
RX_STATUS2-0, PHY_STATUS Delay
(1)(2)
(1) Output Load max = 10 pF, min = 5 pF
(2) Timing is relative to the 50% transition point, not V
IH
/V
IL
.
6.5.4 ULPI Parameters
Table 6-4. ULPI Parameters
DESCRIPTION NOTES HS FS LS UNIT
RX CMD delay 2-4 2-4 2-4 clocks
TX start delay 1-2 1-10 1-10 clocks
TX end delay PHY pipeline delays 2-5 clocks
RX start delay 3-8 clocks
RX end delay 3-8 17-18 122-123 clocks
Transmit-Transmit (host only) 15-24 7-18 77-247 clocks
Link decision times
Receive-Transmit (host or peripheral) 1-14 7-18 77-247 clocks
6.5.5 ULPI Clock
Table 6-5. ULPI Clock Parameters
DESCRIPTION SYMBOL MIN TYP MAX UNITS
Frequency (first transition) ±10% Fstart_8bit 54 60 66 MHz
Frequency (steady state) ±500 ppm Fsteady 59.97 60 60.03 MHz
Duty cycle (first transition) ±10% Dstart_8bit 40 50 60 %
Duty cycle (steady state) ±500 ppm Dsteady 49.97 5 50 50.02 5 %
Time to reach steady state frequency and duty cycle after
Tsteady 1.4 ms
first transition
Clock startup time after deassertion of SuspemdM –
Tstart_dev 5.6 ms
Peripheral
Clock startup time after deassertion of SuspemdM – Hold Tstart_host ms
PHY preparation time after first transition of input clock Tprep µs
Jitter Tjitter ps
34 ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated
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