Datasheet

VDDO1P1
XI
VSSOSC
XO
VDDO1P8
VSSO
CL1
Crystal
VDD1P8
CL2
VDD1P1
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TUSB1310A
www.ti.com
SLLSE32E NOVEMBER 2010REVISED JULY 2012
Load capacitance (C
LOAD
) of the crystal varying with the crystal vendors is the total capacitance value of
the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and
CL2 in Figure 5-4. The trace length between the decoupling capacitors and the corresponding power pins
on the TUSB1310A needs to be minimized. It is also recommended that the trace length from the
capacitor pad to the power or ground plane be minimized.
Figure 5-4. Typical Crystal Connections
5.2 Clock Source Requirements
5.2.1 Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter components, the Reference Clock jitter must be considerably below the overall jitter
budget.
5.2.2 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
Table 5-1. Oscillator Specification
PARAMETER MIN TYP MAX UNITS CONDITION
Frequency tolerance ±50 ppm Operational temperature
Frequency stability ±50 ppm 1 year aging
Rise/Fall time 6 nsec 20% - 80%
Reference clock R
J
0.8 psec
with JTF (1 sigma)
(1)(2)
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
Copyright © 2010–2012, Texas Instruments Incorporated DESIGN GUIDELINES 29
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