Datasheet
TUSB1310A
SLLSE32E –NOVEMBER 2010–REVISED JULY 2012
www.ti.com
4.2.6 USB Interrupt Enable Falling (10h-12h)
Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
Table 4-8. USB Interrupt Enable Falling
BITS NAME ACCESS RESET DESCRIPTION
Generate an interrupt event notification when Host-disconnect
0 Hostdisconnect Fall Rd/Wr/S/C 1b
changes from high to low. Applicable only in host.
4.2.7 USB Interrupt Status (13h)
Address: 13h (Read-only)
Table 4-9. USB Interrupt Status
BITS NAME ACCESS RESET DESCRIPTION
Generate an interrupt event notification when Host-disconnect
0 Hostdisconnect Fall Rd/Wr/S/C 1b
changes from high to low. Applicable only in host.
4.2.8 USB Interrupt Latch (14h)
Address: 14h (Read-only with auto-clear)
Table 4-10. USB Interrupt Latch
BITS NAME ACCESS RESET DESCRIPTION
Set to 1b by the PHY when an unmasked event occurs on
0 Hostdisconnect Fall Rd/Wr/S/C 1b Hostdisconnect. Cleared when this register is read.
Applicable only in host mode.
4.2.9 Debug (15h)
Address: 15h (Read-only)
Table 4-11. Debug
BITS NAME ACCESS RESET DESCRIPTION
0 LineState0 Rd 0 Contains the current value of LineState0
1 LineState1 Rd 0 Contains the current value of LineState1
7:2 Reserved Rd 0 Reserved
4.2.10 Scratch Register (16-18h)
Address: 16-18h (Read), 16h (Write), 17h (Set), 18h (Clear)
Table 4-12. Scratch Register
BITS NAME ACCESS RESET DESCRIPTION
Empty register byte for testing purposes. Software can read,
7:0 Scratch Rd/Wr/S/C 00 write, set, and clear this register and the TUSB1310A
functionality will not be affected.
26 REGISTERS Copyright © 2010–2012, Texas Instruments Incorporated
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